T1 <= '0'; |
FTCPE_XLXN_16: FTCPE port map (XLXN_16,XLXN_16_T,NOT XLXN_19/XLXN_19_CLKF__$INT,XLXN_18/XLXN_18_RSTF,'0'); XLXN_16_T <= (XLXN_18 AND XLXN_17 AND XLXN_19); |
FTCPE_XLXN_17: FTCPE port map (XLXN_17,XLXN_17_T,NOT XLXN_19/XLXN_19_CLKF__$INT,XLXN_18/XLXN_18_RSTF,'0'); XLXN_17_T <= (XLXN_18 AND XLXN_19); |
FTCPE_XLXN_18: FTCPE port map (XLXN_18,XLXN_19,NOT XLXN_19/XLXN_19_CLKF__$INT,XLXN_18/XLXN_18_RSTF,'0'); |
XLXN_18/XLXN_18_RSTF <= ((XLXN_17 AND NOT S1) OR (XLXN_18 AND XLXN_17 AND NOT S2) OR (XLXN_18 AND XLXN_16 AND NOT S3)); |
FTCPE_XLXN_19: FTCPE port map (XLXN_19,'1',NOT XLXN_19/XLXN_19_CLKF__$INT,XLXN_18/XLXN_18_RSTF,'0'); |
XLXN_19/XLXN_19_CLKF__$INT <= ((NOT SYNC) OR (S3 AND S2 AND S1)); |
a <= ((NOT XLXN_18 AND XLXN_17 AND NOT XLXN_19) OR (NOT XLXN_18 AND NOT XLXN_17 AND XLXN_19 AND NOT XLXN_16)); |
b <= ((XLXN_18 AND XLXN_17 AND NOT XLXN_19) OR (NOT XLXN_18 AND XLXN_17 AND XLXN_19)); |
c <= (XLXN_18 AND NOT XLXN_17 AND NOT XLXN_19); |
d <= ((XLXN_18 AND XLXN_17 AND XLXN_19) OR (NOT XLXN_18 AND XLXN_17 AND NOT XLXN_19) OR (NOT XLXN_18 AND NOT XLXN_17 AND XLXN_19 AND NOT XLXN_16)); |
e <= ((XLXN_19) OR (NOT XLXN_18 AND XLXN_17)); |
f <= ((XLXN_18 AND NOT XLXN_17) OR (XLXN_18 AND XLXN_19) OR (NOT XLXN_17 AND XLXN_19 AND NOT XLXN_16)); |
g <= ((XLXN_18 AND XLXN_17 AND XLXN_19) OR (NOT XLXN_18 AND NOT XLXN_17 AND NOT XLXN_16)); |
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |