Timing Report

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Design Name kostka
Device, Speed (SpeedFile Version) XC9572XL, -10 (3.0)
Date Created Wed Oct 22 13:07:59 2008
Created By Timing Report Generator: version G.28
Copyright Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for S1
Clock to Setup (tCYC) 10.000 ns.
Clock Pad to Output Pad Delay (tCO) 25.600 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
S1 71.429 Limited by Clock Pulse Width for S1
S2 71.429 Limited by Clock Pulse Width for S2
S3 71.429 Limited by Clock Pulse Width for S3
SYNC 71.429 Limited by Clock Pulse Width for SYNC

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock S1 to Pad
Destination Pad Clock (edge) to Pad
a 25.600
b 25.600
c 25.600
d 25.600
e 25.600
f 25.600
g 25.600

Clock S2 to Pad
Destination Pad Clock (edge) to Pad
a 25.600
b 25.600
c 25.600
d 25.600
e 25.600
f 25.600
g 25.600

Clock S3 to Pad
Destination Pad Clock (edge) to Pad
a 25.600
b 25.600
c 25.600
d 25.600
e 25.600
f 25.600
g 25.600

Clock SYNC to Pad
Destination Pad Clock (edge) to Pad
a 25.600
b 25.600
c 25.600
d 25.600
e 25.600
f 25.600
g 25.600


Clock to Setup Times for Clocks

Clock to Setup for clock S1
Source Destination Delay
XLXN_17.Q XLXN_16.D 10.000
XLXN_18.Q XLXN_16.D 10.000
XLXN_18.Q XLXN_17.D 10.000
XLXN_19.Q XLXN_16.D 10.000
XLXN_19.Q XLXN_17.D 10.000
XLXN_19.Q XLXN_18.D 10.000

Clock to Setup for clock S2
Source Destination Delay
XLXN_17.Q XLXN_16.D 10.000
XLXN_18.Q XLXN_16.D 10.000
XLXN_18.Q XLXN_17.D 10.000
XLXN_19.Q XLXN_16.D 10.000
XLXN_19.Q XLXN_17.D 10.000
XLXN_19.Q XLXN_18.D 10.000

Clock to Setup for clock S3
Source Destination Delay
XLXN_17.Q XLXN_16.D 10.000
XLXN_18.Q XLXN_16.D 10.000
XLXN_18.Q XLXN_17.D 10.000
XLXN_19.Q XLXN_16.D 10.000
XLXN_19.Q XLXN_17.D 10.000
XLXN_19.Q XLXN_18.D 10.000

Clock to Setup for clock SYNC
Source Destination Delay
XLXN_17.Q XLXN_16.D 10.000
XLXN_18.Q XLXN_16.D 10.000
XLXN_18.Q XLXN_17.D 10.000
XLXN_19.Q XLXN_16.D 10.000
XLXN_19.Q XLXN_17.D 10.000
XLXN_19.Q XLXN_18.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 0
Number of Timing errors: 0
Analysis Completed: Wed Oct 22 13:07:59 2008