FTCPE_Q15: FTCPE port map (Q(15),Q_T(15),SYNC,'0','0'); Q_T(15) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND XLXI_53/Q(12) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND XLXI_53/Q(10) AND XLXI_53/Q(13) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(11) AND XLXI_53/Q(14) AND XLXI_53/Q(3) AND XLXI_53/Q(7)); |
T1 <= '0'; |
FTCPE_XLXI_53/Q0: FTCPE port map (XLXI_53/Q(0),'1',SYNC,'0','0'); |
FTCPE_XLXI_53/Q10: FTCPE port map (XLXI_53/Q(10),XLXI_53/Q_T(10),SYNC,'0','0'); XLXI_53/Q_T(10) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(3) AND XLXI_53/Q(7)); |
FTCPE_XLXI_53/Q11: FTCPE port map (XLXI_53/Q(11),XLXI_53/Q_T(11),SYNC,'0','0'); XLXI_53/Q_T(11) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND XLXI_53/Q(10) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(3) AND XLXI_53/Q(7)); |
FTCPE_XLXI_53/Q12: FTCPE port map (XLXI_53/Q(12),XLXI_53/Q_T(12),SYNC,'0','0'); XLXI_53/Q_T(12) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND XLXI_53/Q(10) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(11) AND XLXI_53/Q(3) AND XLXI_53/Q(7)); |
FTCPE_XLXI_53/Q13: FTCPE port map (XLXI_53/Q(13),XLXI_53/Q_T(13),SYNC,'0','0'); XLXI_53/Q_T(13) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND XLXI_53/Q(12) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND XLXI_53/Q(10) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(11) AND XLXI_53/Q(3) AND XLXI_53/Q(7)); |
FTCPE_XLXI_53/Q14: FTCPE port map (XLXI_53/Q(14),XLXI_53/Q_T(14),SYNC,'0','0'); XLXI_53/Q_T(14) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND XLXI_53/Q(12) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND XLXI_53/Q(10) AND XLXI_53/Q(13) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(11) AND XLXI_53/Q(3) AND XLXI_53/Q(7)); |
FTCPE_XLXI_53/Q1: FTCPE port map (XLXI_53/Q(1),XLXI_53/Q(0),SYNC,'0','0'); |
FTCPE_XLXI_53/Q2: FTCPE port map (XLXI_53/Q(2),XLXI_53/Q_T(2),SYNC,'0','0'); XLXI_53/Q_T(2) <= (XLXI_53/Q(0) AND XLXI_53/Q(1)); |
FTCPE_XLXI_53/Q3: FTCPE port map (XLXI_53/Q(3),XLXI_53/Q_T(3),SYNC,'0','0'); XLXI_53/Q_T(3) <= (XLXI_53/Q(0) AND XLXI_53/Q(1) AND XLXI_53/Q(2)); |
FTCPE_XLXI_53/Q4: FTCPE port map (XLXI_53/Q(4),XLXI_53/Q_T(4),SYNC,'0','0'); XLXI_53/Q_T(4) <= (XLXI_53/Q(0) AND XLXI_53/Q(1) AND XLXI_53/Q(2) AND XLXI_53/Q(3)); |
FTCPE_XLXI_53/Q5: FTCPE port map (XLXI_53/Q(5),XLXI_53/Q_T(5),SYNC,'0','0'); XLXI_53/Q_T(5) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(1) AND XLXI_53/Q(2) AND XLXI_53/Q(3)); |
FTCPE_XLXI_53/Q6: FTCPE port map (XLXI_53/Q(6),XLXI_53/Q_T(6),SYNC,'0','0'); XLXI_53/Q_T(6) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(2) AND XLXI_53/Q(3)); |
FTCPE_XLXI_53/Q7: FTCPE port map (XLXI_53/Q(7),XLXI_53/Q_T(7),SYNC,'0','0'); XLXI_53/Q_T(7) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(3)); |
FTCPE_XLXI_53/Q8: FTCPE port map (XLXI_53/Q(8),XLXI_53/Q_T(8),SYNC,'0','0'); XLXI_53/Q_T(8) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(3) AND XLXI_53/Q(7)); |
FTCPE_XLXI_53/Q9: FTCPE port map (XLXI_53/Q(9),XLXI_53/Q_T(9),SYNC,'0','0'); XLXI_53/Q_T(9) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(3) AND XLXI_53/Q(7)); |
FTCPE_XLXI_57/Q0: FTCPE port map (XLXI_57/Q0,'1',Q(15),'0','0'); |
FDCPE_XLXN_1: FDCPE port map (XLXN_1,XLXN_26,NOT XLXN_87,NOT S1,'0'); |
FDCPE_XLXN_24: FDCPE port map (XLXN_24,NOT XLXN_3,NOT XLXN_87,NOT S1,'0'); |
FDCPE_XLXN_26: FDCPE port map (XLXN_26,XLXN_24,NOT XLXN_87,NOT S1,'0'); |
FDCPE_XLXN_28: FDCPE port map (XLXN_28,XLXN_28_D,NOT XLXN_87,NOT S1,'0'); XLXN_28_D <= XLXN_5 XOR XLXN_28_D <= XLXN_3; |
FDCPE_XLXN_3: FDCPE port map (XLXN_3,XLXN_4,NOT XLXN_87,NOT S1,'0'); |
FDCPE_XLXN_4: FDCPE port map (XLXN_4,XLXN_9,NOT XLXN_87,NOT S1,'0'); |
FDCPE_XLXN_5: FDCPE port map (XLXN_5,XLXN_1,NOT XLXN_87,NOT S1,'0'); |
FDCPE_XLXN_87: FDCPE port map (XLXN_87,S3,XLXN_89,'0','0'); |
FTCPE_XLXN_89: FTCPE port map (XLXN_89,XLXI_57/Q0,Q(15),'0','0'); |
FDCPE_XLXN_9: FDCPE port map (XLXN_9,XLXN_9_D,NOT XLXN_87,NOT S1,'0'); XLXN_9_D <= XLXN_3 XOR XLXN_9_D <= XLXN_28; |
a <= ((NOT XLXN_24 AND XLXN_26 AND XLXN_3) OR (NOT XLXN_24 AND NOT XLXN_26 AND NOT XLXN_3)); |
b <= ((XLXN_24 AND XLXN_26 AND XLXN_3) OR (NOT XLXN_24 AND XLXN_26 AND NOT XLXN_3)); |
c <= (XLXN_24 AND NOT XLXN_26 AND XLXN_3); |
d <= ((XLXN_24 AND XLXN_26 AND NOT XLXN_3) OR (NOT XLXN_24 AND XLXN_26 AND XLXN_3) OR (NOT XLXN_24 AND NOT XLXN_26 AND NOT XLXN_3)); |
e <= ((NOT XLXN_3) OR (NOT XLXN_24 AND XLXN_26)); |
f <= NOT (((NOT XLXN_24 AND XLXN_26) OR (NOT XLXN_24 AND XLXN_3) OR (XLXN_26 AND XLXN_3))); |
g <= ((NOT XLXN_24 AND NOT XLXN_26) OR (XLXN_24 AND XLXN_26 AND NOT XLXN_3)); |
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |