Timing Report

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Design Name kostka_anim
Device, Speed (SpeedFile Version) XC9572XL, -10 (3.0)
Date Created Wed Oct 22 15:21:42 2008
Created By Timing Report Generator: version G.28
Copyright Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for XLXN_151.Q
Clock to Setup (tCYC) 10.000 ns.
Pad to Pad Delay (tPD) 11.000 ns.
Setup to Clock at the Pad (tSU) 6.500 ns.
Clock Pad to Output Pad Delay (tCO) 26.600 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK 111.111 Limited by Clock Pulse Width for CLK
XLXN_151.Q 71.429 Limited by Clock Pulse Width for XLXN_151.Q
S1 71.429 Limited by Clock Pulse Width for S1
S2 71.429 Limited by Clock Pulse Width for S2
S3 71.429 Limited by Clock Pulse Width for S3
SYNC 71.429 Limited by Clock Pulse Width for SYNC

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK
Source Pad Setup to clk (edge) Hold to clk (edge)
SYNC 6.500 0.000


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
segA 21.400
segB 21.400
segC 21.400
segD 21.400
segE 21.400
segF 21.400
segG 21.400

Clock S1 to Pad
Destination Pad Clock (edge) to Pad
segD 26.600
segF 26.600
segA 25.600
segB 25.600
segC 25.600
segE 25.600
segG 25.600

Clock S2 to Pad
Destination Pad Clock (edge) to Pad
segD 26.600
segF 26.600
segA 25.600
segB 25.600
segC 25.600
segE 25.600
segG 25.600

Clock S3 to Pad
Destination Pad Clock (edge) to Pad
segD 26.600
segF 26.600
segA 25.600
segB 25.600
segC 25.600
segE 25.600
segG 25.600

Clock SYNC to Pad
Destination Pad Clock (edge) to Pad
segD 26.600
segF 26.600
segA 25.600
segB 25.600
segC 25.600
segE 25.600
segG 25.600


Clock to Setup Times for Clocks

Clock to Setup for clock XLXN_151.Q
Source Destination Delay
XLXN_145.Q XLXN_146.D 10.000
XLXN_145.Q XLXN_147.D 10.000
XLXN_145.Q XLXN_149.D 10.000
XLXN_146.Q XLXN_147.D 10.000
XLXN_146.Q XLXN_149.D 10.000
XLXN_147.Q XLXN_149.D 10.000

Clock to Setup for clock S1
Source Destination Delay
XLXN_14.Q XLXN_13.D 10.000
XLXN_15.Q XLXN_13.D 10.000
XLXN_15.Q XLXN_14.D 10.000
XLXN_16.Q XLXN_13.D 10.000
XLXN_16.Q XLXN_14.D 10.000
XLXN_16.Q XLXN_15.D 10.000

Clock to Setup for clock S2
Source Destination Delay
XLXN_14.Q XLXN_13.D 10.000
XLXN_15.Q XLXN_13.D 10.000
XLXN_15.Q XLXN_14.D 10.000
XLXN_16.Q XLXN_13.D 10.000
XLXN_16.Q XLXN_14.D 10.000
XLXN_16.Q XLXN_15.D 10.000

Clock to Setup for clock S3
Source Destination Delay
XLXN_14.Q XLXN_13.D 10.000
XLXN_15.Q XLXN_13.D 10.000
XLXN_15.Q XLXN_14.D 10.000
XLXN_16.Q XLXN_13.D 10.000
XLXN_16.Q XLXN_14.D 10.000
XLXN_16.Q XLXN_15.D 10.000

Clock to Setup for clock SYNC
Source Destination Delay
XLXN_14.Q XLXN_13.D 10.000
XLXN_15.Q XLXN_13.D 10.000
XLXN_15.Q XLXN_14.D 10.000
XLXN_16.Q XLXN_13.D 10.000
XLXN_16.Q XLXN_14.D 10.000
XLXN_16.Q XLXN_15.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
S1 segD 11.000
S1 segF 11.000
S2 segD 11.000
S2 segF 11.000
S3 segD 11.000
S3 segF 11.000
S1 segA 10.000
S1 segB 10.000
S1 segC 10.000
S1 segE 10.000
S1 segG 10.000
S2 segA 10.000
S2 segB 10.000
S2 segC 10.000
S2 segE 10.000
S2 segG 10.000
S3 segA 10.000
S3 segB 10.000
S3 segC 10.000
S3 segE 10.000
S3 segG 10.000



Number of paths analyzed: 0
Number of Timing errors: 0
Analysis Completed: Wed Oct 22 15:21:42 2008