T1 <= '0'; |
FDCPE_XLXN_1: FDCPE port map (XLXN_1,NOT XLXN_6,NOT S3,NOT S1,'0'); |
FDCPE_XLXN_10: FDCPE port map (XLXN_10,XLXN_10_D,NOT S3,NOT S1,'0'); XLXN_10_D <= XLXN_8 XOR XLXN_10_D <= XLXN_6; |
FDCPE_XLXN_12: FDCPE port map (XLXN_12,XLXN_12_D,NOT S3,NOT S1,'0'); XLXN_12_D <= XLXN_6 XOR XLXN_12_D <= XLXN_10; |
FDCPE_XLXN_21: FDCPE port map (XLXN_21,XLXN_1,NOT S3,NOT S1,'0'); |
FDCPE_XLXN_3: FDCPE port map (XLXN_3,XLXN_21,NOT S3,NOT S1,'0'); |
FDCPE_XLXN_6: FDCPE port map (XLXN_6,XLXN_7,NOT S3,NOT S1,'0'); |
FDCPE_XLXN_7: FDCPE port map (XLXN_7,XLXN_12,NOT S3,NOT S1,'0'); |
FDCPE_XLXN_8: FDCPE port map (XLXN_8,XLXN_3,NOT S3,NOT S1,'0'); |
a <= ((NOT XLXN_1 AND XLXN_21 AND XLXN_6) OR (NOT XLXN_1 AND NOT XLXN_21 AND NOT XLXN_6)); |
b <= ((XLXN_1 AND XLXN_21 AND XLXN_6) OR (NOT XLXN_1 AND XLXN_21 AND NOT XLXN_6)); |
c <= (XLXN_1 AND NOT XLXN_21 AND XLXN_6); |
d <= ((XLXN_1 AND XLXN_21 AND NOT XLXN_6) OR (NOT XLXN_1 AND XLXN_21 AND XLXN_6) OR (NOT XLXN_1 AND NOT XLXN_21 AND NOT XLXN_6)); |
e <= ((NOT XLXN_6) OR (NOT XLXN_1 AND XLXN_21)); |
f <= NOT (((NOT XLXN_1 AND XLXN_21) OR (NOT XLXN_1 AND XLXN_6) OR (XLXN_21 AND XLXN_6))); |
g <= ((NOT XLXN_1 AND NOT XLXN_21) OR (XLXN_1 AND XLXN_21 AND NOT XLXN_6)); |
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |