Design Name | test_pcb |
Fitting Status | Successful |
SW Version | G.28 |
Device Used | XC9572XL-10-PC44 |
Date | 6-14-2008, 1:33PM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
46/72 (64%) | 81/360 (23%) | 30/72 (42%) | 25/34 (74%) | 48/216 (23%) |
|
|
Total Macrocells Available | 72 |
Registered Macrocells | 30 |
Non-registered Macrocells driving I/O | 16 |
Signal mapped onto global clock net (GCK1) | CLK_GEN |
Signal mapped onto global clock net (GCK2) | CLK_FR |
Signal mapped onto global clock net (GCK3) | CLK |
Macrocells in high performance mode (MCHP) | 46 |
Macrocells in low power mode (MCLP) | 0 |
Total macrocells used (MC) | 46 |