cpldfit: version G.28 Xilinx Inc. Fitter Report Design Name: licznik_auto_kor Date: 10-27-2008, 0:04AM Device Used: XC9572XL-10-PC44 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 25 /72 ( 35%) 51 /360 ( 14%) 24 /72 ( 33%) 9 /34 ( 26%) 50 /216 ( 23%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 3 3 | I/O : 8 20 Output : 5 5 | GCK/IO : 1 2 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 9 9 MACROCELL RESOURCES: Total Macrocells Available 72 Registered Macrocells 24 Non-registered Macrocell driving I/O 0 GLOBAL RESOURCES: Signal 'SYNC' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. POWER DATA: There are 25 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 25 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State LED1 3 7 FB3_11 STD FAST 18 I/O O SET LED2 3 4 FB3_15 STD FAST 20 I/O O SET LED2_OBUF/LED2_OBUF_CLKF 16 7 FB3_1 STD (b) (b) LED3 3 4 FB3_17 STD FAST 22 I/O O SET LED4 3 4 FB3_16 STD FAST 24 I/O O SET LED5 3 4 FB4_5 STD FAST 26 I/O O SET Q<15> 1 15 FB1_18 STD (b) (b) RESET XLXI_38/Q<0> 0 0 FB3_14 STD 19 I/O (b) RESET XLXI_38/Q<10> 1 10 FB4_18 STD (b) (b) RESET XLXI_38/Q<11> 1 11 FB4_17 STD 34 I/O (b) RESET XLXI_38/Q<12> 1 12 FB1_17 STD 9 I/O (b) RESET XLXI_38/Q<13> 1 13 FB1_16 STD (b) (b) RESET XLXI_38/Q<14> 1 14 FB1_15 STD 8 I/O (b) RESET XLXI_38/Q<1> 1 1 FB3_13 STD (b) (b) RESET XLXI_38/Q<2> 1 2 FB3_12 STD (b) (b) RESET XLXI_38/Q<3> 1 3 FB3_10 STD (b) (b) RESET XLXI_38/Q<4> 1 4 FB3_9 STD 14 I/O (b) RESET XLXI_38/Q<5> 1 5 FB3_8 STD 13 I/O (b) RESET XLXI_38/Q<6> 1 6 FB3_7 STD (b) (b) RESET XLXI_38/Q<7> 1 7 FB4_16 STD (b) (b) RESET XLXI_38/Q<8> 1 8 FB4_15 STD 33 I/O (b) RESET XLXI_38/Q<9> 1 9 FB4_14 STD 29 I/O I RESET XLXI_39/Q0 1 1 FB2_16 STD (b) (b) RESET XLXN_101 2 2 FB2_18 STD (b) (b) RESET XLXN_126 2 2 FB2_17 STD 44 I/O (b) RESET ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use S1 FB4_14 29 I/O I S2 FB4_11 28 I/O I S3 FB4_8 27 I/O I SYNC FB1_9 5 GCK/I/O GCK/I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 4 15 15 4 0/0 9 FB2 3 4 4 5 0/0 9 FB3 12 16 16 34 4/0 9 FB4 6 15 15 8 1/0 7 ---- ----- ----- ----- 25 51 5/0 34 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 15/39 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 1 I/O (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 2 I/O (unused) 0 0 0 5 FB1_6 3 I/O (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 4 I/O (unused) 0 0 0 5 FB1_9 5 GCK/I/O GCK/I (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 6 GCK/I/O (unused) 0 0 0 5 FB1_12 (b) (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 0 5 FB1_14 7 GCK/I/O XLXI_38/Q<14> 1 0 0 4 FB1_15 STD 8 I/O (b) XLXI_38/Q<13> 1 0 0 4 FB1_16 STD (b) (b) XLXI_38/Q<12> 1 0 0 4 FB1_17 STD 9 I/O (b) Q<15> 1 0 0 4 FB1_18 STD (b) (b) Signals Used by Logic in Function Block 1: XLXI_38/Q<0> 6: XLXI_38/Q<14> 11: XLXI_38/Q<5> 2: XLXI_38/Q<10> 7: XLXI_38/Q<1> 12: XLXI_38/Q<6> 3: XLXI_38/Q<11> 8: XLXI_38/Q<2> 13: XLXI_38/Q<7> 4: XLXI_38/Q<12> 9: XLXI_38/Q<3> 14: XLXI_38/Q<8> 5: XLXI_38/Q<13> 10: XLXI_38/Q<4> 15: XLXI_38/Q<9> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs XLXI_38/Q<14> XXXXX.XXXXXXXXX......................... 14 14 XLXI_38/Q<13> XXXX..XXXXXXXXX......................... 13 13 XLXI_38/Q<12> XXX...XXXXXXXXX......................... 12 12 Q<15> XXXXXXXXXXXXXXX......................... 15 15 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 4/50 Number of signals used by logic mapping into function block: 4 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 35 I/O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 36 I/O (unused) 0 0 0 5 FB2_6 37 I/O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 38 I/O (unused) 0 0 0 5 FB2_9 39 GSR/I/O (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 40 GTS/I/O (unused) 0 0 0 5 FB2_12 (b) (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 42 GTS/I/O (unused) 0 0 0 5 FB2_15 43 I/O XLXI_39/Q0 1 0 0 4 FB2_16 STD (b) (b) XLXN_126 2 0 0 3 FB2_17 STD 44 I/O (b) XLXN_101 2 0 0 3 FB2_18 STD (b) (b) Signals Used by Logic in Function Block 1: Q<15> 3: XLXI_39/Q0 4: XLXN_101 2: S3 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs XLXI_39/Q0 X....................................... 1 1 XLXN_126 .X.X.................................... 2 2 XLXN_101 X.X..................................... 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 16/38 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use LED2_OBUF/LED2_OBUF_CLKF 16 11<- 0 0 FB3_1 STD (b) (b) (unused) 0 0 /\4 1 FB3_2 11 I/O (b) (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 12 I/O (unused) 0 0 0 5 FB3_6 (b) XLXI_38/Q<6> 1 0 0 4 FB3_7 STD (b) (b) XLXI_38/Q<5> 1 0 0 4 FB3_8 STD 13 I/O (b) XLXI_38/Q<4> 1 0 0 4 FB3_9 STD 14 I/O (b) XLXI_38/Q<3> 1 0 0 4 FB3_10 STD (b) (b) LED1 3 0 0 2 FB3_11 STD 18 I/O O XLXI_38/Q<2> 1 0 0 4 FB3_12 STD (b) (b) XLXI_38/Q<1> 1 0 0 4 FB3_13 STD (b) (b) XLXI_38/Q<0> 0 0 0 5 FB3_14 STD 19 I/O (b) LED2 3 0 0 2 FB3_15 STD 20 I/O O LED4 3 0 0 2 FB3_16 STD 24 I/O O LED3 3 0 \/2 0 FB3_17 STD 22 I/O O (unused) 0 0 \/5 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: LED1 7: S1 12: XLXI_38/Q<2> 2: LED2 8: S2 13: XLXI_38/Q<3> 3: LED2_OBUF/LED2_OBUF_CLKF 9: SYNC 14: XLXI_38/Q<4> 4: LED3 10: XLXI_38/Q<0> 15: XLXI_38/Q<5> 5: LED4 11: XLXI_38/Q<1> 16: XLXN_126 6: LED5 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs LED2_OBUF/LED2_OBUF_CLKF XX.XXX..X......X........................ 7 7 XLXI_38/Q<6> .........XXXXXX......................... 6 6 XLXI_38/Q<5> .........XXXXX.......................... 5 5 XLXI_38/Q<4> .........XXXX........................... 4 4 XLXI_38/Q<3> .........XXX............................ 3 3 LED1 XXXXX.XX................................ 7 7 XLXI_38/Q<2> .........XX............................. 2 2 XLXI_38/Q<1> .........X.............................. 1 1 XLXI_38/Q<0> ........................................ 0 0 LED2 X.X...XX................................ 4 4 LED4 ..XX..XX................................ 4 4 LED3 .XX...XX................................ 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 15/39 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 25 I/O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) LED5 3 0 0 2 FB4_5 STD 26 I/O O (unused) 0 0 0 5 FB4_6 (b) (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 27 I/O I (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 28 I/O I (unused) 0 0 0 5 FB4_12 (b) (unused) 0 0 0 5 FB4_13 (b) XLXI_38/Q<9> 1 0 0 4 FB4_14 STD 29 I/O I XLXI_38/Q<8> 1 0 0 4 FB4_15 STD 33 I/O (b) XLXI_38/Q<7> 1 0 0 4 FB4_16 STD (b) (b) XLXI_38/Q<11> 1 0 0 4 FB4_17 STD 34 I/O (b) XLXI_38/Q<10> 1 0 0 4 FB4_18 STD (b) (b) Signals Used by Logic in Function Block 1: LED2_OBUF/LED2_OBUF_CLKF 6: XLXI_38/Q<10> 11: XLXI_38/Q<5> 2: LED4 7: XLXI_38/Q<1> 12: XLXI_38/Q<6> 3: S1 8: XLXI_38/Q<2> 13: XLXI_38/Q<7> 4: S2 9: XLXI_38/Q<3> 14: XLXI_38/Q<8> 5: XLXI_38/Q<0> 10: XLXI_38/Q<4> 15: XLXI_38/Q<9> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs LED5 XXXX.................................... 4 4 XLXI_38/Q<9> ....X.XXXXXXXX.......................... 9 9 XLXI_38/Q<8> ....X.XXXXXXX........................... 8 8 XLXI_38/Q<7> ....X.XXXXXX............................ 7 7 XLXI_38/Q<11> ....XXXXXXXXXXX......................... 11 11 XLXI_38/Q<10> ....X.XXXXXXXXX......................... 10 10 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. FDCPE_LED1: FDCPE port map (LED1,LED1_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED1_D <= ((NOT S2 AND S1) OR (S1 AND LED1 AND LED2 AND LED3 AND LED4)); FDCPE_LED2: FDCPE port map (LED2,LED2_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED2_D <= ((NOT S2 AND S1) OR (S1 AND NOT LED1)); LED2_OBUF/LED2_OBUF_CLKF <= ((EXP6_.EXP) OR (EXP7_.EXP) OR (SYNC AND NOT LED1 AND NOT LED2) OR (SYNC AND NOT LED1 AND NOT LED3) OR (SYNC AND NOT LED1 AND NOT LED4) OR (SYNC AND NOT LED1 AND NOT LED5) OR (SYNC AND NOT LED3 AND NOT LED5)); FDCPE_LED3: FDCPE port map (LED3,LED3_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED3_D <= ((NOT S2 AND S1) OR (S1 AND NOT LED2)); FDCPE_LED4: FDCPE port map (LED4,LED4_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED4_D <= ((NOT S2 AND S1) OR (S1 AND NOT LED3)); FDCPE_LED5: FDCPE port map (LED5,LED5_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED5_D <= ((NOT S2 AND S1) OR (S1 AND NOT LED4)); FTCPE_Q15: FTCPE port map (Q(15),Q_T(15),SYNC,'0','0'); Q_T(15) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(12) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(13) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(11) AND XLXI_38/Q(14) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); FTCPE_XLXI_38/Q0: FTCPE port map (XLXI_38/Q(0),'1',SYNC,'0','0'); FTCPE_XLXI_38/Q10: FTCPE port map (XLXI_38/Q(10),XLXI_38/Q_T(10),SYNC,'0','0'); XLXI_38/Q_T(10) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); FTCPE_XLXI_38/Q11: FTCPE port map (XLXI_38/Q(11),XLXI_38/Q_T(11),SYNC,'0','0'); XLXI_38/Q_T(11) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); FTCPE_XLXI_38/Q12: FTCPE port map (XLXI_38/Q(12),XLXI_38/Q_T(12),SYNC,'0','0'); XLXI_38/Q_T(12) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(11) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); FTCPE_XLXI_38/Q13: FTCPE port map (XLXI_38/Q(13),XLXI_38/Q_T(13),SYNC,'0','0'); XLXI_38/Q_T(13) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(12) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(11) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); FTCPE_XLXI_38/Q14: FTCPE port map (XLXI_38/Q(14),XLXI_38/Q_T(14),SYNC,'0','0'); XLXI_38/Q_T(14) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(12) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(13) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(11) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); FTCPE_XLXI_38/Q1: FTCPE port map (XLXI_38/Q(1),XLXI_38/Q(0),SYNC,'0','0'); FTCPE_XLXI_38/Q2: FTCPE port map (XLXI_38/Q(2),XLXI_38/Q_T(2),SYNC,'0','0'); XLXI_38/Q_T(2) <= (XLXI_38/Q(0) AND XLXI_38/Q(1)); FTCPE_XLXI_38/Q3: FTCPE port map (XLXI_38/Q(3),XLXI_38/Q_T(3),SYNC,'0','0'); XLXI_38/Q_T(3) <= (XLXI_38/Q(0) AND XLXI_38/Q(1) AND XLXI_38/Q(2)); FTCPE_XLXI_38/Q4: FTCPE port map (XLXI_38/Q(4),XLXI_38/Q_T(4),SYNC,'0','0'); XLXI_38/Q_T(4) <= (XLXI_38/Q(0) AND XLXI_38/Q(1) AND XLXI_38/Q(2) AND XLXI_38/Q(3)); FTCPE_XLXI_38/Q5: FTCPE port map (XLXI_38/Q(5),XLXI_38/Q_T(5),SYNC,'0','0'); XLXI_38/Q_T(5) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(1) AND XLXI_38/Q(2) AND XLXI_38/Q(3)); FTCPE_XLXI_38/Q6: FTCPE port map (XLXI_38/Q(6),XLXI_38/Q_T(6),SYNC,'0','0'); XLXI_38/Q_T(6) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(2) AND XLXI_38/Q(3)); FTCPE_XLXI_38/Q7: FTCPE port map (XLXI_38/Q(7),XLXI_38/Q_T(7),SYNC,'0','0'); XLXI_38/Q_T(7) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3)); FTCPE_XLXI_38/Q8: FTCPE port map (XLXI_38/Q(8),XLXI_38/Q_T(8),SYNC,'0','0'); XLXI_38/Q_T(8) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); FTCPE_XLXI_38/Q9: FTCPE port map (XLXI_38/Q(9),XLXI_38/Q_T(9),SYNC,'0','0'); XLXI_38/Q_T(9) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); FTCPE_XLXI_39/Q0: FTCPE port map (XLXI_39/Q0,'1',Q(15),'0','0'); FTCPE_XLXN_101: FTCPE port map (XLXN_101,XLXI_39/Q0,Q(15),'0','0'); FDCPE_XLXN_126: FDCPE port map (XLXN_126,S3,XLXN_101,'0','0'); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); **************************** Device Pin Out **************************** Device : XC9572XL-10-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572XL-10-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 TIE 23 GND 2 TIE 24 LED4 3 TIE 25 TIE 4 TIE 26 LED5 5 SYNC 27 S3 6 TIE 28 S2 7 TIE 29 S1 8 TIE 30 TDO 9 TIE 31 GND 10 GND 32 VCC 11 TIE 33 TIE 12 TIE 34 TIE 13 TIE 35 TIE 14 TIE 36 TIE 15 TDI 37 TIE 16 TMS 38 TIE 17 TCK 39 TIE 18 LED1 40 TIE 19 TIE 41 VCC 20 LED2 42 TIE 21 VCC 43 TIE 22 LED3 44 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25