cpldfit:  version G.28                              Xilinx Inc.
                                  Fitter Report
Design Name: kostka                              Date: 10-22-2008,  8:30PM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
14 /72  ( 19%) 31  /360  (  9%) 4  /72  (  6%) 12 /34  ( 35%) 17 /216 (  8%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    4           4    |  I/O              :     9       19
Output        :    8           8    |  GCK/IO           :     1        2
Bidirectional :    0           0    |  GTS/IO           :     1        1
GCK           :    0           0    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     12          12

MACROCELL RESOURCES:

Total Macrocells Available                    72
Registered Macrocells                          4
Non-registered Macrocell driving I/O           8

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 14 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 14 macrocells used (MC).

End of Resource Summary
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin       Reg Init
Name                Pt      Used            Mode Rate #    Type      Use       State
T1                  0       0       FB2_14  STD  SLOW 42   GTS/I/O   O         
XLXN_16             3       5       FB1_18  STD            (b)       (b)       RESET
XLXN_17             3       4       FB1_17  STD       9    I/O       (b)       RESET
XLXN_18             3       3       FB1_16  STD            (b)       (b)       RESET
XLXN_18/XLXN_18_RSTF                    3       6       FB1_15  STD       8    I/O       (b)       
XLXN_19             2       2       FB1_14  STD       7    GCK/I/O   (b)       RESET
XLXN_19/XLXN_19_CLKF__$INT                    2       4       FB1_13  STD            (b)       (b)       
a                   2       4       FB2_6   STD  SLOW 37   I/O       O         
b                   2       3       FB2_8   STD  SLOW 38   I/O       O         
c                   1       3       FB4_15  STD  SLOW 33   I/O       O         
d                   3       4       FB2_5   STD  SLOW 36   I/O       O         
e                   2       3       FB2_2   STD  SLOW 35   I/O       O         
f                   3       4       FB1_2   STD  SLOW 1    I/O       O         
g                   2       4       FB2_9   STD  SLOW 39   GSR/I/O   O         

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
S1                                  FB4_14            29   I/O       I
S2                                  FB4_11            28   I/O       I
S3                                  FB4_8             27   I/O       I
SYNC                                FB1_9             5    GCK/I/O   I

End of Resources

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           7          10          10           19         1/0        9   
FB2           6           4           4           11         6/0        9   
FB3           0           0           0            0         0/0        9   
FB4           1           3           3            1         1/0        7   
            ----                                -----       -----     ----- 
             14                                   31         8/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               10/44
Number of signals used by logic mapping into function block:  10
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB1_1               (b)     
f                     3       0     0   2     FB1_2   STD   1     I/O     O
(unused)              0       0     0   5     FB1_3               (b)     
(unused)              0       0     0   5     FB1_4               (b)     
(unused)              0       0     0   5     FB1_5         2     I/O     
(unused)              0       0     0   5     FB1_6         3     I/O     
(unused)              0       0     0   5     FB1_7               (b)     
(unused)              0       0     0   5     FB1_8         4     I/O     
(unused)              0       0     0   5     FB1_9         5     GCK/I/O I
(unused)              0       0     0   5     FB1_10              (b)     
(unused)              0       0     0   5     FB1_11        6     GCK/I/O 
(unused)              0       0     0   5     FB1_12              (b)     
XLXN_19/XLXN_19_CLKF__$INT
                      2       0     0   3     FB1_13  STD         (b)     (b)
XLXN_19               2       0     0   3     FB1_14  STD   7     GCK/I/O (b)
XLXN_18/XLXN_18_RSTF
                      3       0     0   2     FB1_15  STD   8     I/O     (b)
XLXN_18               3       0     0   2     FB1_16  STD         (b)     (b)
XLXN_17               3       0     0   2     FB1_17  STD   9     I/O     (b)
XLXN_16               3       0     0   2     FB1_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: S1                 5: XLXN_16            8: XLXN_18/XLXN_18_RSTF 
  2: S2                 6: XLXN_17            9: XLXN_19 
  3: S3                 7: XLXN_18           10: XLXN_19/XLXN_19_CLKF__$INT 
  4: SYNC             

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
f                    ....XXX.X............................... 4       4
XLXN_19/XLXN_19_CLKF__$INT 
                     XXXX.................................... 4       4
XLXN_19              .......X.X.............................. 2       2
XLXN_18/XLXN_18_RSTF 
                     XXX.XXX................................. 6       6
XLXN_18              .......XXX.............................. 3       3
XLXN_17              ......XXXX.............................. 4       4
XLXN_16              .....XXXXX.............................. 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               4/50
Number of signals used by logic mapping into function block:  4
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1               (b)     
e                     2       0     0   3     FB2_2   STD   35    I/O     O
(unused)              0       0     0   5     FB2_3               (b)     
(unused)              0       0     0   5     FB2_4               (b)     
d                     3       0     0   2     FB2_5   STD   36    I/O     O
a                     2       0     0   3     FB2_6   STD   37    I/O     O
(unused)              0       0     0   5     FB2_7               (b)     
b                     2       0     0   3     FB2_8   STD   38    I/O     O
g                     2       0     0   3     FB2_9   STD   39    GSR/I/O O
(unused)              0       0     0   5     FB2_10              (b)     
(unused)              0       0     0   5     FB2_11        40    GTS/I/O 
(unused)              0       0     0   5     FB2_12              (b)     
(unused)              0       0     0   5     FB2_13              (b)     
T1                    0       0     0   5     FB2_14  STD   42    GTS/I/O O
(unused)              0       0     0   5     FB2_15        43    I/O     
(unused)              0       0     0   5     FB2_16              (b)     
(unused)              0       0     0   5     FB2_17        44    I/O     
(unused)              0       0     0   5     FB2_18              (b)     

Signals Used by Logic in Function Block
  1: XLXN_16            3: XLXN_18            4: XLXN_19 
  2: XLXN_17          

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
e                    .XXX.................................... 3       3
d                    XXXX.................................... 4       4
a                    XXXX.................................... 4       4
b                    .XXX.................................... 3       3
g                    XXXX.................................... 4       4
T1                   ........................................ 0       0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB3_1               (b)     
(unused)              0       0     0   5     FB3_2         11    I/O     
(unused)              0       0     0   5     FB3_3               (b)     
(unused)              0       0     0   5     FB3_4               (b)     
(unused)              0       0     0   5     FB3_5         12    I/O     
(unused)              0       0     0   5     FB3_6               (b)     
(unused)              0       0     0   5     FB3_7               (b)     
(unused)              0       0     0   5     FB3_8         13    I/O     
(unused)              0       0     0   5     FB3_9         14    I/O     
(unused)              0       0     0   5     FB3_10              (b)     
(unused)              0       0     0   5     FB3_11        18    I/O     
(unused)              0       0     0   5     FB3_12              (b)     
(unused)              0       0     0   5     FB3_13              (b)     
(unused)              0       0     0   5     FB3_14        19    I/O     
(unused)              0       0     0   5     FB3_15        20    I/O     
(unused)              0       0     0   5     FB3_16        24    I/O     
(unused)              0       0     0   5     FB3_17        22    I/O     
(unused)              0       0     0   5     FB3_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               3/51
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB4_1               (b)     
(unused)              0       0     0   5     FB4_2         25    I/O     
(unused)              0       0     0   5     FB4_3               (b)     
(unused)              0       0     0   5     FB4_4               (b)     
(unused)              0       0     0   5     FB4_5         26    I/O     
(unused)              0       0     0   5     FB4_6               (b)     
(unused)              0       0     0   5     FB4_7               (b)     
(unused)              0       0     0   5     FB4_8         27    I/O     I
(unused)              0       0     0   5     FB4_9               (b)     
(unused)              0       0     0   5     FB4_10              (b)     
(unused)              0       0     0   5     FB4_11        28    I/O     I
(unused)              0       0     0   5     FB4_12              (b)     
(unused)              0       0     0   5     FB4_13              (b)     
(unused)              0       0     0   5     FB4_14        29    I/O     I
c                     1       0     0   4     FB4_15  STD   33    I/O     O
(unused)              0       0     0   5     FB4_16              (b)     
(unused)              0       0     0   5     FB4_17        34    I/O     
(unused)              0       0     0   5     FB4_18              (b)     

Signals Used by Logic in Function Block
  1: XLXN_17            2: XLXN_18            3: XLXN_19 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
c                    XXX..................................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.


T1 <= '0';

FTCPE_XLXN_16: FTCPE port map (XLXN_16,XLXN_16_T,NOT XLXN_19/XLXN_19_CLKF__$INT,XLXN_18/XLXN_18_RSTF,'0');
XLXN_16_T <= (XLXN_18 AND XLXN_17 AND XLXN_19);

FTCPE_XLXN_17: FTCPE port map (XLXN_17,XLXN_17_T,NOT XLXN_19/XLXN_19_CLKF__$INT,XLXN_18/XLXN_18_RSTF,'0');
XLXN_17_T <= (XLXN_18 AND XLXN_19);

FTCPE_XLXN_18: FTCPE port map (XLXN_18,XLXN_19,NOT XLXN_19/XLXN_19_CLKF__$INT,XLXN_18/XLXN_18_RSTF,'0');


XLXN_18/XLXN_18_RSTF <= ((XLXN_17 AND NOT S1)
	OR (XLXN_18 AND XLXN_17 AND NOT S2)
	OR (XLXN_18 AND XLXN_16 AND NOT S3));

FTCPE_XLXN_19: FTCPE port map (XLXN_19,'1',NOT XLXN_19/XLXN_19_CLKF__$INT,XLXN_18/XLXN_18_RSTF,'0');


XLXN_19/XLXN_19_CLKF__$INT <= ((NOT SYNC)
	OR (S3 AND S2 AND S1));


a <= ((NOT XLXN_18 AND XLXN_17 AND NOT XLXN_19)
	OR (NOT XLXN_18 AND NOT XLXN_17 AND XLXN_19 AND NOT XLXN_16));


b <= ((XLXN_18 AND XLXN_17 AND NOT XLXN_19)
	OR (NOT XLXN_18 AND XLXN_17 AND XLXN_19));


c <= (XLXN_18 AND NOT XLXN_17 AND NOT XLXN_19);


d <= ((XLXN_18 AND XLXN_17 AND XLXN_19)
	OR (NOT XLXN_18 AND XLXN_17 AND NOT XLXN_19)
	OR (NOT XLXN_18 AND NOT XLXN_17 AND XLXN_19 AND NOT XLXN_16));


e <= ((XLXN_19)
	OR (NOT XLXN_18 AND XLXN_17));


f <= ((XLXN_18 AND NOT XLXN_17)
	OR (XLXN_18 AND XLXN_19)
	OR (NOT XLXN_17 AND XLXN_19 AND NOT XLXN_16));


g <= ((XLXN_18 AND XLXN_17 AND XLXN_19)
	OR (NOT XLXN_18 AND NOT XLXN_17 AND NOT XLXN_16));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

****************************  Device Pin Out ****************************

Device : XC9572XL-10-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XC9572XL-10-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 f                                23 GND                           
  2 TIE                              24 TIE                           
  3 TIE                              25 TIE                           
  4 TIE                              26 TIE                           
  5 SYNC                             27 S3                            
  6 TIE                              28 S2                            
  7 TIE                              29 S1                            
  8 TIE                              30 TDO                           
  9 TIE                              31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 c                             
 12 TIE                              34 TIE                           
 13 TIE                              35 e                             
 14 TIE                              36 d                             
 15 TDI                              37 a                             
 16 TMS                              38 b                             
 17 TCK                              39 g                             
 18 TIE                              40 TIE                           
 19 TIE                              41 VCC                           
 20 TIE                              42 T1                            
 21 VCC                              43 TIE                           
 22 TIE                              44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : STD
Set Unused I/O Pin Termination              : FLOAT
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25