cpldfit:  version G.28                              Xilinx Inc.
                                  Fitter Report
Design Name: minutnik                            Date: 10-28-2008,  1:36PM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
66 /72  ( 92%) 153 /360  ( 42%) 59 /72  ( 82%) 10 /34  ( 29%) 79 /216 ( 37%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    2           2    |  I/O              :     8       20
Output        :    7           7    |  GCK/IO           :     1        2
Bidirectional :    0           0    |  GTS/IO           :     1        1
GCK           :    1           1    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     10          10

MACROCELL RESOURCES:

Total Macrocells Available                    72
Registered Macrocells                         59
Non-registered Macrocell driving I/O           2

GLOBAL RESOURCES:

Signal 'SYNC' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 66 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 66 macrocells used (MC).

End of Resource Summary
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin       Reg Init
Name                Pt      Used            Mode Rate #    Type      Use       State
LED1                2       5       FB3_11  STD  FAST 18   I/O       O         SET
LED2                2       2       FB3_15  STD  FAST 20   I/O       O         SET
LED2_OBUF/LED2_OBUF_CLKF                    16      7       FB4_1   STD            (b)       (b)       
LED3                2       2       FB3_17  STD  FAST 22   I/O       O         SET
LED4                2       2       FB3_16  STD  FAST 24   I/O       O         SET
LED5                2       2       FB4_5   STD  FAST 26   I/O       O         SET
Q1<3>               3       5       FB1_18  STD            (b)       (b)       RESET
Q1<6>               3       8       FB1_17  STD       9    I/O       (b)       RESET
Q1<7>               3       9       FB1_16  STD            (b)       (b)       RESET
Q2<3>               3       5       FB1_15  STD       8    I/O       (b)       RESET
Q2<6>               3       8       FB1_14  STD       7    GCK/I/O   (b)       RESET
Q2<7>               3       9       FB1_13  STD            (b)       (b)       RESET
Q3<3>               2       4       FB2_18  STD            (b)       (b)       RESET
Q3<6>               2       7       FB2_17  STD       44   I/O       (b)       RESET
Q3<7>               2       8       FB2_16  STD            (b)       (b)       RESET
Q4<2>               3       4       FB4_16  STD            (b)       (b)       RESET
Q4<4>               3       6       FB4_15  STD       33   I/O       (b)       RESET
Q4<5>               3       7       FB4_14  STD       29   I/O       I         RESET
Q4<7>               3       9       FB4_13  STD            (b)       (b)       RESET
T1                  0       0       FB2_14  STD  FAST 42   GTS/I/O   O         
XLXI_1/Q<15>        1       15      FB3_18  STD            (b)       (b)       RESET
XLXI_1/XLXI_38/Q<0> 0       0       FB2_8   STD       38   I/O       (b)       RESET
XLXI_1/XLXI_38/Q<10>                    1       10      FB3_14  STD       19   I/O       (b)       RESET
XLXI_1/XLXI_38/Q<11>                    1       11      FB3_13  STD            (b)       (b)       RESET
XLXI_1/XLXI_38/Q<12>                    1       12      FB3_12  STD            (b)       (b)       RESET
XLXI_1/XLXI_38/Q<13>                    1       13      FB3_10  STD            (b)       (b)       RESET
XLXI_1/XLXI_38/Q<14>                    1       14      FB3_9   STD       14   I/O       (b)       RESET
XLXI_1/XLXI_38/Q<1> 1       1       FB2_7   STD            (b)       (b)       RESET
XLXI_1/XLXI_38/Q<2> 1       2       FB3_8   STD       13   I/O       (b)       RESET
XLXI_1/XLXI_38/Q<3> 1       3       FB3_7   STD            (b)       (b)       RESET
XLXI_1/XLXI_38/Q<4> 1       4       FB3_6   STD            (b)       (b)       RESET
XLXI_1/XLXI_38/Q<5> 1       5       FB3_5   STD       12   I/O       (b)       RESET
XLXI_1/XLXI_38/Q<6> 1       6       FB3_4   STD            (b)       (b)       RESET
XLXI_1/XLXI_38/Q<7> 1       7       FB3_3   STD            (b)       (b)       RESET
XLXI_1/XLXI_38/Q<8> 1       8       FB3_2   STD       11   I/O       (b)       RESET
XLXI_1/XLXI_38/Q<9> 1       9       FB3_1   STD            (b)       (b)       RESET
XLXI_1/XLXI_39/Q0   1       1       FB2_6   STD       37   I/O       (b)       RESET
XLXI_1/XLXN_101     2       2       FB2_15  STD       43   I/O       (b)       RESET
XLXI_1/XLXN_126     2       2       FB2_13  STD            (b)       (b)       RESET
XLXI_54/Q<0>        2       2       FB1_4   STD            (b)       (b)       RESET
XLXI_54/Q<1>        3       3       FB1_12  STD            (b)       (b)       RESET
XLXI_54/Q<2>        3       4       FB1_11  STD       6    GCK/I/O   (b)       RESET
XLXI_54/Q<4>        3       6       FB1_10  STD            (b)       (b)       RESET
XLXI_54/Q<5>        3       7       FB1_9   STD       5    GCK/I/O   GCK/I     RESET
XLXI_54/Q<5>/XLXI_54/Q<5>_RSTF                    2       4       FB1_3   STD            (b)       (b)       
XLXI_56/Q<0>        1       1       FB4_18  STD            (b)       (b)       RESET
XLXI_56/Q<1>        2       2       FB2_12  STD            (b)       (b)       RESET
XLXI_56/Q<2>        2       3       FB2_11  STD       40   GTS/I/O   (b)       RESET
XLXI_56/Q<4>        2       5       FB2_10  STD            (b)       (b)       RESET
XLXI_56/Q<5>        2       6       FB2_9   STD       39   GSR/I/O   (b)       RESET
XLXI_56/Q<5>/XLXI_56/Q<5>_RSTF                    2       4       FB1_2   STD       1    I/O       (b)       
XLXI_58/Q<0>        2       2       FB1_1   STD            (b)       (b)       RESET
XLXI_58/Q<1>        3       3       FB1_8   STD       4    I/O       (b)       RESET
XLXI_58/Q<2>        3       4       FB1_7   STD            (b)       (b)       RESET
XLXI_58/Q<4>        3       6       FB1_6   STD       3    I/O       (b)       RESET
XLXI_58/Q<5>        3       7       FB1_5   STD       2    I/O       (b)       RESET
XLXI_58/Q<5>/XLXI_58/Q<5>_RSTF                    2       4       FB4_7   STD            (b)       (b)       
XLXI_73/Q<0>        2       2       FB4_6   STD            (b)       (b)       RESET
XLXI_73/Q<1>        3       3       FB4_12  STD            (b)       (b)       RESET
XLXI_73/Q<3>        3       5       FB4_11  STD       28   I/O       (b)       RESET
XLXI_73/Q<6>        3       8       FB4_10  STD            (b)       (b)       RESET
XLXI_73/Q<6>/XLXI_73/Q<6>_RSTF                    2       5       FB4_4   STD            (b)       (b)       
XLXN_72             2       2       FB4_3   STD            (b)       (b)       RESET
XLXN_73             3       3       FB4_9   STD            (b)       (b)       RESET
XLXN_74             3       4       FB4_8   STD       27   I/O       I         RESET
segDP               7       8       FB4_17  STD  FAST 34   I/O       O         

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
S1                                  FB4_14            29   I/O       I
S3                                  FB4_8             27   I/O       I
SYNC                                FB1_9             5    GCK/I/O   GCK/I

End of Resources

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          18          21          21           50         0/0        9   
FB2          13          13          13           20         1/0        9   
FB3          18          20          20           22         4/0        9   
FB4          17          25          25           61         2/0        7   
            ----                                -----       -----     ----- 
             66                                  153         7/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               21/33
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
XLXI_58/Q<0>          2       0     0   3     FB1_1   STD         (b)     (b)
XLXI_56/Q<5>/XLXI_56/Q<5>_RSTF
                      2       0     0   3     FB1_2   STD   1     I/O     (b)
XLXI_54/Q<5>/XLXI_54/Q<5>_RSTF
                      2       0     0   3     FB1_3   STD         (b)     (b)
XLXI_54/Q<0>          2       0     0   3     FB1_4   STD         (b)     (b)
XLXI_58/Q<5>          3       0     0   2     FB1_5   STD   2     I/O     (b)
XLXI_58/Q<4>          3       0     0   2     FB1_6   STD   3     I/O     (b)
XLXI_58/Q<2>          3       0     0   2     FB1_7   STD         (b)     (b)
XLXI_58/Q<1>          3       0     0   2     FB1_8   STD   4     I/O     (b)
XLXI_54/Q<5>          3       0     0   2     FB1_9   STD   5     GCK/I/O GCK/I
XLXI_54/Q<4>          3       0     0   2     FB1_10  STD         (b)     (b)
XLXI_54/Q<2>          3       0     0   2     FB1_11  STD   6     GCK/I/O (b)
XLXI_54/Q<1>          3       0     0   2     FB1_12  STD         (b)     (b)
Q2<7>                 3       0     0   2     FB1_13  STD         (b)     (b)
Q2<6>                 3       0     0   2     FB1_14  STD   7     GCK/I/O (b)
Q2<3>                 3       0     0   2     FB1_15  STD   8     I/O     (b)
Q1<7>                 3       0     0   2     FB1_16  STD         (b)     (b)
Q1<6>                 3       0     0   2     FB1_17  STD   9     I/O     (b)
Q1<3>                 3       0     0   2     FB1_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: Q1<3>              8: Q3<7>             15: XLXI_54/Q<5>/XLXI_54/Q<5>_RSTF 
  2: Q1<6>              9: S3                16: XLXI_58/Q<0> 
  3: Q2<3>             10: XLXI_54/Q<0>      17: XLXI_58/Q<1> 
  4: Q2<6>             11: XLXI_54/Q<1>      18: XLXI_58/Q<2> 
  5: Q2<7>             12: XLXI_54/Q<2>      19: XLXI_58/Q<4> 
  6: Q3<3>             13: XLXI_54/Q<4>      20: XLXI_58/Q<5> 
  7: Q3<6>             14: XLXI_54/Q<5>      21: XLXI_58/Q<5>/XLXI_58/Q<5>_RSTF 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
XLXI_58/Q<0>         ....X...............X................... 2       2
XLXI_56/Q<5>/XLXI_56/Q<5>_RSTF 
                     .....XXXX............................... 4       4
XLXI_54/Q<5>/XLXI_54/Q<5>_RSTF 
                     ..XXX...X............................... 4       4
XLXI_54/Q<0>         .......X......X......................... 2       2
XLXI_58/Q<5>         X...X..........XXXX.X................... 7       7
XLXI_58/Q<4>         X...X..........XXX..X................... 6       6
XLXI_58/Q<2>         ....X..........XX...X................... 4       4
XLXI_58/Q<1>         ....X..........X....X................... 3       3
XLXI_54/Q<5>         ..X....X.XXXX.X......................... 7       7
XLXI_54/Q<4>         ..X....X.XXX..X......................... 6       6
XLXI_54/Q<2>         .......X.XX...X......................... 4       4
XLXI_54/Q<1>         .......X.X....X......................... 3       3
Q2<7>                ..XX...X.XXXXXX......................... 9       9
Q2<6>                ..X....X.XXXXXX......................... 8       8
Q2<3>                .......X.XXX..X......................... 5       5
Q1<7>                XX..X..........XXXXXX................... 9       9
Q1<6>                X...X..........XXXXXX................... 8       8
Q1<3>                ....X..........XXX..X................... 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               13/41
Number of signals used by logic mapping into function block:  13
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1               (b)     
(unused)              0       0     0   5     FB2_2         35    I/O     
(unused)              0       0     0   5     FB2_3               (b)     
(unused)              0       0     0   5     FB2_4               (b)     
(unused)              0       0     0   5     FB2_5         36    I/O     
XLXI_1/XLXI_39/Q0     1       0     0   4     FB2_6   STD   37    I/O     (b)
XLXI_1/XLXI_38/Q<1>   1       0     0   4     FB2_7   STD         (b)     (b)
XLXI_1/XLXI_38/Q<0>   0       0     0   5     FB2_8   STD   38    I/O     (b)
XLXI_56/Q<5>          2       0     0   3     FB2_9   STD   39    GSR/I/O (b)
XLXI_56/Q<4>          2       0     0   3     FB2_10  STD         (b)     (b)
XLXI_56/Q<2>          2       0     0   3     FB2_11  STD   40    GTS/I/O (b)
XLXI_56/Q<1>          2       0     0   3     FB2_12  STD         (b)     (b)
XLXI_1/XLXN_126       2       0     0   3     FB2_13  STD         (b)     (b)
T1                    0       0     0   5     FB2_14  STD   42    GTS/I/O O
XLXI_1/XLXN_101       2       0     0   3     FB2_15  STD   43    I/O     (b)
Q3<7>                 2       0     0   3     FB2_16  STD         (b)     (b)
Q3<6>                 2       0     0   3     FB2_17  STD   44    I/O     (b)
Q3<3>                 2       0     0   3     FB2_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: Q3<3>              6: XLXI_1/XLXI_39/Q0 10: XLXI_56/Q<2> 
  2: Q3<6>              7: XLXI_1/XLXN_101   11: XLXI_56/Q<4> 
  3: S1                 8: XLXI_56/Q<0>      12: XLXI_56/Q<5> 
  4: XLXI_1/Q<15>       9: XLXI_56/Q<1>      13: XLXI_56/Q<5>/XLXI_56/Q<5>_RSTF 
  5: XLXI_1/XLXI_38/Q<0> 
                      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
XLXI_1/XLXI_39/Q0    ...X.................................... 1       1
XLXI_1/XLXI_38/Q<1>  ....X................................... 1       1
XLXI_1/XLXI_38/Q<0>  ........................................ 0       0
XLXI_56/Q<5>         X......XXXX.X........................... 6       6
XLXI_56/Q<4>         X......XXX..X........................... 5       5
XLXI_56/Q<2>         .......XX...X........................... 3       3
XLXI_56/Q<1>         .......X....X........................... 2       2
XLXI_1/XLXN_126      ..X...X................................. 2       2
T1                   ........................................ 0       0
XLXI_1/XLXN_101      ...X.X.................................. 2       2
Q3<7>                XX.....XXXXXX........................... 8       8
Q3<6>                X......XXXXXX........................... 7       7
Q3<3>                .......XXX..X........................... 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               20/34
Number of signals used by logic mapping into function block:  20
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
XLXI_1/XLXI_38/Q<9>   1       0     0   4     FB3_1   STD         (b)     (b)
XLXI_1/XLXI_38/Q<8>   1       0     0   4     FB3_2   STD   11    I/O     (b)
XLXI_1/XLXI_38/Q<7>   1       0     0   4     FB3_3   STD         (b)     (b)
XLXI_1/XLXI_38/Q<6>   1       0     0   4     FB3_4   STD         (b)     (b)
XLXI_1/XLXI_38/Q<5>   1       0     0   4     FB3_5   STD   12    I/O     (b)
XLXI_1/XLXI_38/Q<4>   1       0     0   4     FB3_6   STD         (b)     (b)
XLXI_1/XLXI_38/Q<3>   1       0     0   4     FB3_7   STD         (b)     (b)
XLXI_1/XLXI_38/Q<2>   1       0     0   4     FB3_8   STD   13    I/O     (b)
XLXI_1/XLXI_38/Q<14>
                      1       0     0   4     FB3_9   STD   14    I/O     (b)
XLXI_1/XLXI_38/Q<13>
                      1       0     0   4     FB3_10  STD         (b)     (b)
LED1                  2       0     0   3     FB3_11  STD   18    I/O     O
XLXI_1/XLXI_38/Q<12>
                      1       0     0   4     FB3_12  STD         (b)     (b)
XLXI_1/XLXI_38/Q<11>
                      1       0     0   4     FB3_13  STD         (b)     (b)
XLXI_1/XLXI_38/Q<10>
                      1       0     0   4     FB3_14  STD   19    I/O     (b)
LED2                  2       0     0   3     FB3_15  STD   20    I/O     O
LED4                  2       0     0   3     FB3_16  STD   24    I/O     O
LED3                  2       0     0   3     FB3_17  STD   22    I/O     O
XLXI_1/Q<15>          1       0     0   4     FB3_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: LED1               8: XLXI_1/XLXI_38/Q<11> 
                                             15: XLXI_1/XLXI_38/Q<4> 
  2: LED2               9: XLXI_1/XLXI_38/Q<12> 
                                             16: XLXI_1/XLXI_38/Q<5> 
  3: LED2_OBUF/LED2_OBUF_CLKF 
                       10: XLXI_1/XLXI_38/Q<13> 
                                             17: XLXI_1/XLXI_38/Q<6> 
  4: LED3              11: XLXI_1/XLXI_38/Q<14> 
                                             18: XLXI_1/XLXI_38/Q<7> 
  5: LED4              12: XLXI_1/XLXI_38/Q<1> 
                                             19: XLXI_1/XLXI_38/Q<8> 
  6: XLXI_1/XLXI_38/Q<0> 
                       13: XLXI_1/XLXI_38/Q<2> 
                                             20: XLXI_1/XLXI_38/Q<9> 
  7: XLXI_1/XLXI_38/Q<10> 
                       14: XLXI_1/XLXI_38/Q<3> 
                                            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
XLXI_1/XLXI_38/Q<9>  .....X.....XXXXXXXX..................... 9       9
XLXI_1/XLXI_38/Q<8>  .....X.....XXXXXXX...................... 8       8
XLXI_1/XLXI_38/Q<7>  .....X.....XXXXXX....................... 7       7
XLXI_1/XLXI_38/Q<6>  .....X.....XXXXX........................ 6       6
XLXI_1/XLXI_38/Q<5>  .....X.....XXXX......................... 5       5
XLXI_1/XLXI_38/Q<4>  .....X.....XXX.......................... 4       4
XLXI_1/XLXI_38/Q<3>  .....X.....XX........................... 3       3
XLXI_1/XLXI_38/Q<2>  .....X.....X............................ 2       2
XLXI_1/XLXI_38/Q<14> 
                     .....XXXXX.XXXXXXXXX.................... 14      14
XLXI_1/XLXI_38/Q<13> 
                     .....XXXX..XXXXXXXXX.................... 13      13
LED1                 XXXXX................................... 5       5
XLXI_1/XLXI_38/Q<12> 
                     .....XXX...XXXXXXXXX.................... 12      12
XLXI_1/XLXI_38/Q<11> 
                     .....XX....XXXXXXXXX.................... 11      11
XLXI_1/XLXI_38/Q<10> 
                     .....X.....XXXXXXXXX.................... 10      10
LED2                 X.X..................................... 2       2
LED4                 ..XX.................................... 2       2
LED3                 .XX..................................... 2       2
XLXI_1/Q<15>         .....XXXXXXXXXXXXXXX.................... 15      15
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               25/29
Number of signals used by logic mapping into function block:  25
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
LED2_OBUF/LED2_OBUF_CLKF
                     16      11<-   0   0     FB4_1   STD         (b)     (b)
(unused)              0       0   /\5   0     FB4_2         25    I/O     (b)
XLXN_72               2       0   /\2   1     FB4_3   STD         (b)     (b)
XLXI_73/Q<6>/XLXI_73/Q<6>_RSTF
                      2       0     0   3     FB4_4   STD         (b)     (b)
LED5                  2       0     0   3     FB4_5   STD   26    I/O     O
XLXI_73/Q<0>          2       0     0   3     FB4_6   STD         (b)     (b)
XLXI_58/Q<5>/XLXI_58/Q<5>_RSTF
                      2       0     0   3     FB4_7   STD         (b)     (b)
XLXN_74               3       0     0   2     FB4_8   STD   27    I/O     I
XLXN_73               3       0     0   2     FB4_9   STD         (b)     (b)
XLXI_73/Q<6>          3       0     0   2     FB4_10  STD         (b)     (b)
XLXI_73/Q<3>          3       0     0   2     FB4_11  STD   28    I/O     (b)
XLXI_73/Q<1>          3       0     0   2     FB4_12  STD         (b)     (b)
Q4<7>                 3       0     0   2     FB4_13  STD         (b)     (b)
Q4<5>                 3       0     0   2     FB4_14  STD   29    I/O     I
Q4<4>                 3       0     0   2     FB4_15  STD   33    I/O     (b)
Q4<2>                 3       0   \/2   0     FB4_16  STD         (b)     (b)
segDP                 7       2<-   0   0     FB4_17  STD   34    I/O     O
XLXI_56/Q<0>          1       0   \/4   0     FB4_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: LED1              10: Q4<2>             18: XLXI_73/Q<0> 
  2: LED2              11: Q4<4>             19: XLXI_73/Q<1> 
  3: LED2_OBUF/LED2_OBUF_CLKF 
                       12: Q4<5>             20: XLXI_73/Q<3> 
  4: LED3              13: Q4<7>             21: XLXI_73/Q<6> 
  5: LED4              14: S3                22: XLXI_73/Q<6>/XLXI_73/Q<6>_RSTF 
  6: LED5              15: SYNC              23: XLXN_72 
  7: Q1<3>             16: XLXI_1/XLXN_126   24: XLXN_73 
  8: Q1<6>             17: XLXI_56/Q<5>/XLXI_56/Q<5>_RSTF 
                                             25: XLXN_74 
  9: Q1<7>            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LED2_OBUF/LED2_OBUF_CLKF 
                     XX.XXX........XX........................ 7       7
XLXN_72              ............XX.......................... 2       2
XLXI_73/Q<6>/XLXI_73/Q<6>_RSTF 
                     .........XXXXX.......................... 5       5
LED5                 ..X.X................................... 2       2
XLXI_73/Q<0>         ........X............X.................. 2       2
XLXI_58/Q<5>/XLXI_58/Q<5>_RSTF 
                     ......XXX....X.......................... 4       4
XLXN_74              ............XX........XX................ 4       4
XLXN_73              ............XX........X................. 3       3
XLXI_73/Q<6>         ........XXXX.....XXX.X.................. 8       8
XLXI_73/Q<3>         ........XX.......XX..X.................. 5       5
XLXI_73/Q<1>         ........X........X...X.................. 3       3
Q4<7>                ........XXXX.....XXXXX.................. 9       9
Q4<5>                ........XXX......XXX.X.................. 7       7
Q4<4>                ........XX.......XXX.X.................. 6       6
Q4<2>                ........X........XX..X.................. 4       4
segDP                XX.XXX................XXX............... 8       8
XLXI_56/Q<0>         ................X....................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.



FDCPE_LED1: FDCPE port map (LED1,LED1_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0');
LED1_D <= (LED1 AND LED2 AND LED3 AND LED4);

FDCPE_LED2: FDCPE port map (LED2,LED1,LED2_OBUF/LED2_OBUF_CLKF,'0','0');


LED2_OBUF/LED2_OBUF_CLKF <= ((EXP6_.EXP)
	OR (XLXI_56/Q(0).EXP)
	OR (SYNC AND NOT LED1 AND NOT LED2)
	OR (SYNC AND NOT LED1 AND NOT LED3)
	OR (SYNC AND NOT LED1 AND NOT LED4)
	OR (SYNC AND NOT LED1 AND NOT LED5)
	OR (SYNC AND NOT LED3 AND NOT LED5));

FDCPE_LED3: FDCPE port map (LED3,LED2,LED2_OBUF/LED2_OBUF_CLKF,'0','0');

FDCPE_LED4: FDCPE port map (LED4,LED3,LED2_OBUF/LED2_OBUF_CLKF,'0','0');

FDCPE_LED5: FDCPE port map (LED5,LED4,LED2_OBUF/LED2_OBUF_CLKF,'0','0');

FTCPE_Q13: FTCPE port map (Q1(3),Q1_T(3),Q2(7),XLXI_58/Q(5)/XLXI_58/Q(5)_RSTF,'0');
Q1_T(3) <= (XLXI_58/Q(0) AND XLXI_58/Q(1) AND XLXI_58/Q(2));

FTCPE_Q16: FTCPE port map (Q1(6),Q1_T(6),Q2(7),XLXI_58/Q(5)/XLXI_58/Q(5)_RSTF,'0');
Q1_T(6) <= (XLXI_58/Q(0) AND XLXI_58/Q(1) AND XLXI_58/Q(4) AND 
	Q1(3) AND XLXI_58/Q(2) AND XLXI_58/Q(5));

FTCPE_Q17: FTCPE port map (Q1(7),Q1_T(7),Q2(7),XLXI_58/Q(5)/XLXI_58/Q(5)_RSTF,'0');
Q1_T(7) <= (XLXI_58/Q(0) AND XLXI_58/Q(1) AND XLXI_58/Q(4) AND 
	Q1(3) AND Q1(6) AND XLXI_58/Q(2) AND XLXI_58/Q(5));

FTCPE_Q23: FTCPE port map (Q2(3),Q2_T(3),Q3(7),XLXI_54/Q(5)/XLXI_54/Q(5)_RSTF,'0');
Q2_T(3) <= (XLXI_54/Q(0) AND XLXI_54/Q(1) AND XLXI_54/Q(2));

FTCPE_Q26: FTCPE port map (Q2(6),Q2_T(6),Q3(7),XLXI_54/Q(5)/XLXI_54/Q(5)_RSTF,'0');
Q2_T(6) <= (XLXI_54/Q(0) AND XLXI_54/Q(1) AND XLXI_54/Q(4) AND 
	Q2(3) AND XLXI_54/Q(2) AND XLXI_54/Q(5));

FTCPE_Q27: FTCPE port map (Q2(7),Q2_T(7),Q3(7),XLXI_54/Q(5)/XLXI_54/Q(5)_RSTF,'0');
Q2_T(7) <= (XLXI_54/Q(0) AND XLXI_54/Q(1) AND XLXI_54/Q(4) AND 
	Q2(3) AND Q2(6) AND XLXI_54/Q(2) AND XLXI_54/Q(5));

FTCPE_Q33: FTCPE port map (Q3(3),Q3_T(3),SYNC,XLXI_56/Q(5)/XLXI_56/Q(5)_RSTF,'0');
Q3_T(3) <= (XLXI_56/Q(0) AND XLXI_56/Q(1) AND XLXI_56/Q(2));

FTCPE_Q36: FTCPE port map (Q3(6),Q3_T(6),SYNC,XLXI_56/Q(5)/XLXI_56/Q(5)_RSTF,'0');
Q3_T(6) <= (XLXI_56/Q(0) AND XLXI_56/Q(1) AND XLXI_56/Q(4) AND 
	Q3(3) AND XLXI_56/Q(2) AND XLXI_56/Q(5));

FTCPE_Q37: FTCPE port map (Q3(7),Q3_T(7),SYNC,XLXI_56/Q(5)/XLXI_56/Q(5)_RSTF,'0');
Q3_T(7) <= (XLXI_56/Q(0) AND XLXI_56/Q(1) AND XLXI_56/Q(4) AND 
	Q3(3) AND Q3(6) AND XLXI_56/Q(2) AND XLXI_56/Q(5));

FTCPE_Q42: FTCPE port map (Q4(2),Q4_T(2),Q1(7),XLXI_73/Q(6)/XLXI_73/Q(6)_RSTF,'0');
Q4_T(2) <= (XLXI_73/Q(0) AND XLXI_73/Q(1));

FTCPE_Q44: FTCPE port map (Q4(4),Q4_T(4),Q1(7),XLXI_73/Q(6)/XLXI_73/Q(6)_RSTF,'0');
Q4_T(4) <= (XLXI_73/Q(0) AND Q4(2) AND XLXI_73/Q(1) AND 
	XLXI_73/Q(3));

FTCPE_Q45: FTCPE port map (Q4(5),Q4_T(5),Q1(7),XLXI_73/Q(6)/XLXI_73/Q(6)_RSTF,'0');
Q4_T(5) <= (Q4(4) AND XLXI_73/Q(0) AND Q4(2) AND XLXI_73/Q(1) AND 
	XLXI_73/Q(3));

FTCPE_Q47: FTCPE port map (Q4(7),Q4_T(7),Q1(7),XLXI_73/Q(6)/XLXI_73/Q(6)_RSTF,'0');
Q4_T(7) <= (Q4(4) AND XLXI_73/Q(0) AND Q4(2) AND Q4(5) AND 
	XLXI_73/Q(1) AND XLXI_73/Q(3) AND XLXI_73/Q(6));


T1 <= '0';

FTCPE_XLXI_1/Q15: FTCPE port map (XLXI_1/Q(15),XLXI_1/Q_T(15),SYNC,'0','0');
XLXI_1/Q_T(15) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(8) AND XLXI_1/XLXI_38/Q(12) AND XLXI_1/XLXI_38/Q(1) AND 
	XLXI_1/XLXI_38/Q(5) AND XLXI_1/XLXI_38/Q(9) AND XLXI_1/XLXI_38/Q(10) AND 
	XLXI_1/XLXI_38/Q(13) AND XLXI_1/XLXI_38/Q(2) AND XLXI_1/XLXI_38/Q(6) AND 
	XLXI_1/XLXI_38/Q(11) AND XLXI_1/XLXI_38/Q(14) AND XLXI_1/XLXI_38/Q(3) AND 
	XLXI_1/XLXI_38/Q(7));

FTCPE_XLXI_1/XLXI_38/Q0: FTCPE port map (XLXI_1/XLXI_38/Q(0),'1',SYNC,'0','0');

FTCPE_XLXI_1/XLXI_38/Q10: FTCPE port map (XLXI_1/XLXI_38/Q(10),XLXI_1/XLXI_38/Q_T(10),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(10) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(8) AND XLXI_1/XLXI_38/Q(1) AND XLXI_1/XLXI_38/Q(5) AND 
	XLXI_1/XLXI_38/Q(9) AND XLXI_1/XLXI_38/Q(2) AND XLXI_1/XLXI_38/Q(6) AND 
	XLXI_1/XLXI_38/Q(3) AND XLXI_1/XLXI_38/Q(7));

FTCPE_XLXI_1/XLXI_38/Q11: FTCPE port map (XLXI_1/XLXI_38/Q(11),XLXI_1/XLXI_38/Q_T(11),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(11) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(8) AND XLXI_1/XLXI_38/Q(1) AND XLXI_1/XLXI_38/Q(5) AND 
	XLXI_1/XLXI_38/Q(9) AND XLXI_1/XLXI_38/Q(10) AND XLXI_1/XLXI_38/Q(2) AND 
	XLXI_1/XLXI_38/Q(6) AND XLXI_1/XLXI_38/Q(3) AND XLXI_1/XLXI_38/Q(7));

FTCPE_XLXI_1/XLXI_38/Q12: FTCPE port map (XLXI_1/XLXI_38/Q(12),XLXI_1/XLXI_38/Q_T(12),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(12) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(8) AND XLXI_1/XLXI_38/Q(1) AND XLXI_1/XLXI_38/Q(5) AND 
	XLXI_1/XLXI_38/Q(9) AND XLXI_1/XLXI_38/Q(10) AND XLXI_1/XLXI_38/Q(2) AND 
	XLXI_1/XLXI_38/Q(6) AND XLXI_1/XLXI_38/Q(11) AND XLXI_1/XLXI_38/Q(3) AND 
	XLXI_1/XLXI_38/Q(7));

FTCPE_XLXI_1/XLXI_38/Q13: FTCPE port map (XLXI_1/XLXI_38/Q(13),XLXI_1/XLXI_38/Q_T(13),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(13) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(8) AND XLXI_1/XLXI_38/Q(12) AND XLXI_1/XLXI_38/Q(1) AND 
	XLXI_1/XLXI_38/Q(5) AND XLXI_1/XLXI_38/Q(9) AND XLXI_1/XLXI_38/Q(10) AND 
	XLXI_1/XLXI_38/Q(2) AND XLXI_1/XLXI_38/Q(6) AND XLXI_1/XLXI_38/Q(11) AND 
	XLXI_1/XLXI_38/Q(3) AND XLXI_1/XLXI_38/Q(7));

FTCPE_XLXI_1/XLXI_38/Q14: FTCPE port map (XLXI_1/XLXI_38/Q(14),XLXI_1/XLXI_38/Q_T(14),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(14) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(8) AND XLXI_1/XLXI_38/Q(12) AND XLXI_1/XLXI_38/Q(1) AND 
	XLXI_1/XLXI_38/Q(5) AND XLXI_1/XLXI_38/Q(9) AND XLXI_1/XLXI_38/Q(10) AND 
	XLXI_1/XLXI_38/Q(13) AND XLXI_1/XLXI_38/Q(2) AND XLXI_1/XLXI_38/Q(6) AND 
	XLXI_1/XLXI_38/Q(11) AND XLXI_1/XLXI_38/Q(3) AND XLXI_1/XLXI_38/Q(7));

FTCPE_XLXI_1/XLXI_38/Q1: FTCPE port map (XLXI_1/XLXI_38/Q(1),XLXI_1/XLXI_38/Q(0),SYNC,'0','0');

FTCPE_XLXI_1/XLXI_38/Q2: FTCPE port map (XLXI_1/XLXI_38/Q(2),XLXI_1/XLXI_38/Q_T(2),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(2) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(1));

FTCPE_XLXI_1/XLXI_38/Q3: FTCPE port map (XLXI_1/XLXI_38/Q(3),XLXI_1/XLXI_38/Q_T(3),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(3) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(1) AND 
	XLXI_1/XLXI_38/Q(2));

FTCPE_XLXI_1/XLXI_38/Q4: FTCPE port map (XLXI_1/XLXI_38/Q(4),XLXI_1/XLXI_38/Q_T(4),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(4) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(1) AND 
	XLXI_1/XLXI_38/Q(2) AND XLXI_1/XLXI_38/Q(3));

FTCPE_XLXI_1/XLXI_38/Q5: FTCPE port map (XLXI_1/XLXI_38/Q(5),XLXI_1/XLXI_38/Q_T(5),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(5) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(1) AND XLXI_1/XLXI_38/Q(2) AND XLXI_1/XLXI_38/Q(3));

FTCPE_XLXI_1/XLXI_38/Q6: FTCPE port map (XLXI_1/XLXI_38/Q(6),XLXI_1/XLXI_38/Q_T(6),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(6) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(1) AND XLXI_1/XLXI_38/Q(5) AND XLXI_1/XLXI_38/Q(2) AND 
	XLXI_1/XLXI_38/Q(3));

FTCPE_XLXI_1/XLXI_38/Q7: FTCPE port map (XLXI_1/XLXI_38/Q(7),XLXI_1/XLXI_38/Q_T(7),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(7) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(1) AND XLXI_1/XLXI_38/Q(5) AND XLXI_1/XLXI_38/Q(2) AND 
	XLXI_1/XLXI_38/Q(6) AND XLXI_1/XLXI_38/Q(3));

FTCPE_XLXI_1/XLXI_38/Q8: FTCPE port map (XLXI_1/XLXI_38/Q(8),XLXI_1/XLXI_38/Q_T(8),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(8) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(1) AND XLXI_1/XLXI_38/Q(5) AND XLXI_1/XLXI_38/Q(2) AND 
	XLXI_1/XLXI_38/Q(6) AND XLXI_1/XLXI_38/Q(3) AND XLXI_1/XLXI_38/Q(7));

FTCPE_XLXI_1/XLXI_38/Q9: FTCPE port map (XLXI_1/XLXI_38/Q(9),XLXI_1/XLXI_38/Q_T(9),SYNC,'0','0');
XLXI_1/XLXI_38/Q_T(9) <= (XLXI_1/XLXI_38/Q(0) AND XLXI_1/XLXI_38/Q(4) AND 
	XLXI_1/XLXI_38/Q(8) AND XLXI_1/XLXI_38/Q(1) AND XLXI_1/XLXI_38/Q(5) AND 
	XLXI_1/XLXI_38/Q(2) AND XLXI_1/XLXI_38/Q(6) AND XLXI_1/XLXI_38/Q(3) AND 
	XLXI_1/XLXI_38/Q(7));

FTCPE_XLXI_1/XLXI_39/Q0: FTCPE port map (XLXI_1/XLXI_39/Q0,'1',XLXI_1/Q(15),'0','0');

FTCPE_XLXI_1/XLXN_101: FTCPE port map (XLXI_1/XLXN_101,XLXI_1/XLXI_39/Q0,XLXI_1/Q(15),'0','0');

FDCPE_XLXI_1/XLXN_126: FDCPE port map (XLXI_1/XLXN_126,S1,XLXI_1/XLXN_101,'0','0');

FTCPE_XLXI_54/Q0: FTCPE port map (XLXI_54/Q(0),'1',Q3(7),XLXI_54/Q(5)/XLXI_54/Q(5)_RSTF,'0');

FTCPE_XLXI_54/Q1: FTCPE port map (XLXI_54/Q(1),XLXI_54/Q(0),Q3(7),XLXI_54/Q(5)/XLXI_54/Q(5)_RSTF,'0');

FTCPE_XLXI_54/Q2: FTCPE port map (XLXI_54/Q(2),XLXI_54/Q_T(2),Q3(7),XLXI_54/Q(5)/XLXI_54/Q(5)_RSTF,'0');
XLXI_54/Q_T(2) <= (XLXI_54/Q(0) AND XLXI_54/Q(1));

FTCPE_XLXI_54/Q4: FTCPE port map (XLXI_54/Q(4),XLXI_54/Q_T(4),Q3(7),XLXI_54/Q(5)/XLXI_54/Q(5)_RSTF,'0');
XLXI_54/Q_T(4) <= (XLXI_54/Q(0) AND XLXI_54/Q(1) AND Q2(3) AND 
	XLXI_54/Q(2));

FTCPE_XLXI_54/Q5: FTCPE port map (XLXI_54/Q(5),XLXI_54/Q_T(5),Q3(7),XLXI_54/Q(5)/XLXI_54/Q(5)_RSTF,'0');
XLXI_54/Q_T(5) <= (XLXI_54/Q(0) AND XLXI_54/Q(1) AND XLXI_54/Q(4) AND 
	Q2(3) AND XLXI_54/Q(2));


XLXI_54/Q(5)/XLXI_54/Q(5)_RSTF <= ((NOT S3)
	OR (Q2(7) AND Q2(3) AND Q2(6)));

FTCPE_XLXI_56/Q0: FTCPE port map (XLXI_56/Q(0),'1',SYNC,XLXI_56/Q(5)/XLXI_56/Q(5)_RSTF,'0');

FTCPE_XLXI_56/Q1: FTCPE port map (XLXI_56/Q(1),XLXI_56/Q(0),SYNC,XLXI_56/Q(5)/XLXI_56/Q(5)_RSTF,'0');

FTCPE_XLXI_56/Q2: FTCPE port map (XLXI_56/Q(2),XLXI_56/Q_T(2),SYNC,XLXI_56/Q(5)/XLXI_56/Q(5)_RSTF,'0');
XLXI_56/Q_T(2) <= (XLXI_56/Q(0) AND XLXI_56/Q(1));

FTCPE_XLXI_56/Q4: FTCPE port map (XLXI_56/Q(4),XLXI_56/Q_T(4),SYNC,XLXI_56/Q(5)/XLXI_56/Q(5)_RSTF,'0');
XLXI_56/Q_T(4) <= (XLXI_56/Q(0) AND XLXI_56/Q(1) AND Q3(3) AND 
	XLXI_56/Q(2));

FTCPE_XLXI_56/Q5: FTCPE port map (XLXI_56/Q(5),XLXI_56/Q_T(5),SYNC,XLXI_56/Q(5)/XLXI_56/Q(5)_RSTF,'0');
XLXI_56/Q_T(5) <= (XLXI_56/Q(0) AND XLXI_56/Q(1) AND XLXI_56/Q(4) AND 
	Q3(3) AND XLXI_56/Q(2));


XLXI_56/Q(5)/XLXI_56/Q(5)_RSTF <= ((NOT S3)
	OR (Q3(7) AND Q3(3) AND Q3(6)));

FTCPE_XLXI_58/Q0: FTCPE port map (XLXI_58/Q(0),'1',Q2(7),XLXI_58/Q(5)/XLXI_58/Q(5)_RSTF,'0');

FTCPE_XLXI_58/Q1: FTCPE port map (XLXI_58/Q(1),XLXI_58/Q(0),Q2(7),XLXI_58/Q(5)/XLXI_58/Q(5)_RSTF,'0');

FTCPE_XLXI_58/Q2: FTCPE port map (XLXI_58/Q(2),XLXI_58/Q_T(2),Q2(7),XLXI_58/Q(5)/XLXI_58/Q(5)_RSTF,'0');
XLXI_58/Q_T(2) <= (XLXI_58/Q(0) AND XLXI_58/Q(1));

FTCPE_XLXI_58/Q4: FTCPE port map (XLXI_58/Q(4),XLXI_58/Q_T(4),Q2(7),XLXI_58/Q(5)/XLXI_58/Q(5)_RSTF,'0');
XLXI_58/Q_T(4) <= (XLXI_58/Q(0) AND XLXI_58/Q(1) AND Q1(3) AND 
	XLXI_58/Q(2));

FTCPE_XLXI_58/Q5: FTCPE port map (XLXI_58/Q(5),XLXI_58/Q_T(5),Q2(7),XLXI_58/Q(5)/XLXI_58/Q(5)_RSTF,'0');
XLXI_58/Q_T(5) <= (XLXI_58/Q(0) AND XLXI_58/Q(1) AND XLXI_58/Q(4) AND 
	Q1(3) AND XLXI_58/Q(2));


XLXI_58/Q(5)/XLXI_58/Q(5)_RSTF <= ((NOT S3)
	OR (Q1(7) AND Q1(3) AND Q1(6)));

FTCPE_XLXI_73/Q0: FTCPE port map (XLXI_73/Q(0),'1',Q1(7),XLXI_73/Q(6)/XLXI_73/Q(6)_RSTF,'0');

FTCPE_XLXI_73/Q1: FTCPE port map (XLXI_73/Q(1),XLXI_73/Q(0),Q1(7),XLXI_73/Q(6)/XLXI_73/Q(6)_RSTF,'0');

FTCPE_XLXI_73/Q3: FTCPE port map (XLXI_73/Q(3),XLXI_73/Q_T(3),Q1(7),XLXI_73/Q(6)/XLXI_73/Q(6)_RSTF,'0');
XLXI_73/Q_T(3) <= (XLXI_73/Q(0) AND Q4(2) AND XLXI_73/Q(1));

FTCPE_XLXI_73/Q6: FTCPE port map (XLXI_73/Q(6),XLXI_73/Q_T(6),Q1(7),XLXI_73/Q(6)/XLXI_73/Q(6)_RSTF,'0');
XLXI_73/Q_T(6) <= (Q4(4) AND XLXI_73/Q(0) AND Q4(2) AND Q4(5) AND 
	XLXI_73/Q(1) AND XLXI_73/Q(3));


XLXI_73/Q(6)/XLXI_73/Q(6)_RSTF <= ((NOT S3)
	OR (Q4(4) AND Q4(7) AND Q4(2) AND Q4(5)));

FTCPE_XLXN_72: FTCPE port map (XLXN_72,'1',NOT Q4(7),NOT S3,'0');

FTCPE_XLXN_73: FTCPE port map (XLXN_73,XLXN_72,NOT Q4(7),NOT S3,'0');

FTCPE_XLXN_74: FTCPE port map (XLXN_74,XLXN_74_T,NOT Q4(7),NOT S3,'0');
XLXN_74_T <= (XLXN_72 AND XLXN_73);


segDP <= NOT (((Q4(2).EXP)
	OR (XLXN_73 AND XLXN_74 AND LED1 AND LED2 AND LED3 AND LED4 AND 
	LED5)
	OR (XLXN_72 AND XLXN_73 AND NOT XLXN_74 AND LED1 AND LED2 AND 
	NOT LED3 AND LED4 AND LED5)
	OR (XLXN_72 AND NOT XLXN_73 AND NOT XLXN_74 AND NOT LED1 AND LED2 AND 
	LED3 AND LED4 AND LED5)
	OR (NOT XLXN_72 AND XLXN_73 AND NOT XLXN_74 AND LED1 AND NOT LED2 AND 
	LED3 AND LED4 AND LED5)
	OR (NOT XLXN_72 AND NOT XLXN_73 AND NOT XLXN_74 AND LED1 AND LED2 AND 
	LED3 AND LED4 AND LED5)));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

****************************  Device Pin Out ****************************

Device : XC9572XL-10-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XC9572XL-10-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              23 GND                           
  2 TIE                              24 LED4                          
  3 TIE                              25 TIE                           
  4 TIE                              26 LED5                          
  5 SYNC                             27 S3                            
  6 TIE                              28 TIE                           
  7 TIE                              29 S1                            
  8 TIE                              30 TDO                           
  9 TIE                              31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 TIE                           
 12 TIE                              34 segDP                         
 13 TIE                              35 TIE                           
 14 TIE                              36 TIE                           
 15 TDI                              37 TIE                           
 16 TMS                              38 TIE                           
 17 TCK                              39 TIE                           
 18 LED1                             40 TIE                           
 19 TIE                              41 VCC                           
 20 LED2                             42 T1                            
 21 VCC                              43 TIE                           
 22 LED3                             44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Set Unused I/O Pin Termination              : FLOAT
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25