FDCPE_LED1: FDCPE port map (LED1,LED1_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED1_D <= ((NOT S2 AND S1) OR (S1 AND LED1 AND LED2 AND LED3 AND LED4)); |
FDCPE_LED2: FDCPE port map (LED2,LED2_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED2_D <= ((NOT S2 AND S1) OR (S1 AND NOT LED1)); |
LED2_OBUF/LED2_OBUF_CLKF <= ((EXP6_.EXP) OR (EXP7_.EXP) OR (SYNC AND NOT LED1 AND NOT LED2) OR (SYNC AND NOT LED1 AND NOT LED3) OR (SYNC AND NOT LED1 AND NOT LED4) OR (SYNC AND NOT LED1 AND NOT LED5) OR (SYNC AND NOT LED3 AND NOT LED5)); |
FDCPE_LED3: FDCPE port map (LED3,LED3_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED3_D <= ((NOT S2 AND S1) OR (S1 AND NOT LED2)); |
FDCPE_LED4: FDCPE port map (LED4,LED4_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED4_D <= ((NOT S2 AND S1) OR (S1 AND NOT LED3)); |
FDCPE_LED5: FDCPE port map (LED5,LED5_D,LED2_OBUF/LED2_OBUF_CLKF,'0','0'); LED5_D <= ((NOT S2 AND S1) OR (S1 AND NOT LED4)); |
FTCPE_Q15: FTCPE port map (Q(15),Q_T(15),SYNC,'0','0'); Q_T(15) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(12) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(13) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(11) AND XLXI_38/Q(14) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); |
FTCPE_XLXI_38/Q0: FTCPE port map (XLXI_38/Q(0),'1',SYNC,'0','0'); |
FTCPE_XLXI_38/Q10: FTCPE port map (XLXI_38/Q(10),XLXI_38/Q_T(10),SYNC,'0','0'); XLXI_38/Q_T(10) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); |
FTCPE_XLXI_38/Q11: FTCPE port map (XLXI_38/Q(11),XLXI_38/Q_T(11),SYNC,'0','0'); XLXI_38/Q_T(11) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); |
FTCPE_XLXI_38/Q12: FTCPE port map (XLXI_38/Q(12),XLXI_38/Q_T(12),SYNC,'0','0'); XLXI_38/Q_T(12) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(11) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); |
FTCPE_XLXI_38/Q13: FTCPE port map (XLXI_38/Q(13),XLXI_38/Q_T(13),SYNC,'0','0'); XLXI_38/Q_T(13) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(12) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(11) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); |
FTCPE_XLXI_38/Q14: FTCPE port map (XLXI_38/Q(14),XLXI_38/Q_T(14),SYNC,'0','0'); XLXI_38/Q_T(14) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(12) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(9) AND XLXI_38/Q(10) AND XLXI_38/Q(13) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(11) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); |
FTCPE_XLXI_38/Q1: FTCPE port map (XLXI_38/Q(1),XLXI_38/Q(0),SYNC,'0','0'); |
FTCPE_XLXI_38/Q2: FTCPE port map (XLXI_38/Q(2),XLXI_38/Q_T(2),SYNC,'0','0'); XLXI_38/Q_T(2) <= (XLXI_38/Q(0) AND XLXI_38/Q(1)); |
FTCPE_XLXI_38/Q3: FTCPE port map (XLXI_38/Q(3),XLXI_38/Q_T(3),SYNC,'0','0'); XLXI_38/Q_T(3) <= (XLXI_38/Q(0) AND XLXI_38/Q(1) AND XLXI_38/Q(2)); |
FTCPE_XLXI_38/Q4: FTCPE port map (XLXI_38/Q(4),XLXI_38/Q_T(4),SYNC,'0','0'); XLXI_38/Q_T(4) <= (XLXI_38/Q(0) AND XLXI_38/Q(1) AND XLXI_38/Q(2) AND XLXI_38/Q(3)); |
FTCPE_XLXI_38/Q5: FTCPE port map (XLXI_38/Q(5),XLXI_38/Q_T(5),SYNC,'0','0'); XLXI_38/Q_T(5) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(1) AND XLXI_38/Q(2) AND XLXI_38/Q(3)); |
FTCPE_XLXI_38/Q6: FTCPE port map (XLXI_38/Q(6),XLXI_38/Q_T(6),SYNC,'0','0'); XLXI_38/Q_T(6) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(2) AND XLXI_38/Q(3)); |
FTCPE_XLXI_38/Q7: FTCPE port map (XLXI_38/Q(7),XLXI_38/Q_T(7),SYNC,'0','0'); XLXI_38/Q_T(7) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3)); |
FTCPE_XLXI_38/Q8: FTCPE port map (XLXI_38/Q(8),XLXI_38/Q_T(8),SYNC,'0','0'); XLXI_38/Q_T(8) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); |
FTCPE_XLXI_38/Q9: FTCPE port map (XLXI_38/Q(9),XLXI_38/Q_T(9),SYNC,'0','0'); XLXI_38/Q_T(9) <= (XLXI_38/Q(0) AND XLXI_38/Q(4) AND XLXI_38/Q(8) AND XLXI_38/Q(1) AND XLXI_38/Q(5) AND XLXI_38/Q(2) AND XLXI_38/Q(6) AND XLXI_38/Q(3) AND XLXI_38/Q(7)); |
FTCPE_XLXI_39/Q0: FTCPE port map (XLXI_39/Q0,'1',Q(15),'0','0'); |
FTCPE_XLXN_101: FTCPE port map (XLXN_101,XLXI_39/Q0,Q(15),'0','0'); |
FDCPE_XLXN_126: FDCPE port map (XLXN_126,S3,XLXN_101,'0','0'); |
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |