cpldfit:  version G.28                              Xilinx Inc.
                                  Fitter Report
Design Name: lfsr_ext                            Date: 10-25-2008,  6:30PM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
35 /72  ( 49%) 61  /360  ( 17%) 27 /72  ( 37%) 11 /34  ( 32%) 52 /216 ( 24%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    2           2    |  I/O              :     8       20
Output        :    8           8    |  GCK/IO           :     1        2
Bidirectional :    0           0    |  GTS/IO           :     1        1
GCK           :    1           1    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     11          11

MACROCELL RESOURCES:

Total Macrocells Available                    72
Registered Macrocells                         27
Non-registered Macrocell driving I/O           8

GLOBAL RESOURCES:

Signal 'SYNC' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 35 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 35 macrocells used (MC).

End of Resource Summary
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin       Reg Init
Name                Pt      Used            Mode Rate #    Type      Use       State
Q<15>               1       15      FB3_18  STD            (b)       (b)       RESET
T1                  0       0       FB2_14  STD  SLOW 42   GTS/I/O   O         
XLXI_53/Q<0>        0       0       FB1_10  STD            (b)       (b)       RESET
XLXI_53/Q<10>       1       10      FB2_18  STD            (b)       (b)       RESET
XLXI_53/Q<11>       1       11      FB2_17  STD       44   I/O       (b)       RESET
XLXI_53/Q<12>       1       12      FB2_16  STD            (b)       (b)       RESET
XLXI_53/Q<13>       1       13      FB3_17  STD       22   I/O       (b)       RESET
XLXI_53/Q<14>       1       14      FB3_16  STD       24   I/O       (b)       RESET
XLXI_53/Q<1>        1       1       FB1_9   STD       5    GCK/I/O   GCK       RESET
XLXI_53/Q<2>        1       2       FB1_8   STD       4    I/O       (b)       RESET
XLXI_53/Q<3>        1       3       FB1_7   STD            (b)       (b)       RESET
XLXI_53/Q<4>        1       4       FB1_6   STD       3    I/O       (b)       RESET
XLXI_53/Q<5>        1       5       FB1_5   STD       2    I/O       (b)       RESET
XLXI_53/Q<6>        1       6       FB2_15  STD       43   I/O       (b)       RESET
XLXI_53/Q<7>        1       7       FB2_13  STD            (b)       (b)       RESET
XLXI_53/Q<8>        1       8       FB2_12  STD            (b)       (b)       RESET
XLXI_53/Q<9>        1       9       FB2_11  STD       40   GTS/I/O   (b)       RESET
XLXI_57/Q0          1       1       FB4_16  STD            (b)       (b)       RESET
XLXN_1              3       3       FB1_16  STD            (b)       (b)       RESET
XLXN_24             3       3       FB1_15  STD       8    I/O       (b)       RESET
XLXN_26             3       3       FB1_14  STD       7    GCK/I/O   (b)       RESET
XLXN_28             4       4       FB1_18  STD            (b)       (b)       RESET
XLXN_3              3       3       FB1_13  STD            (b)       (b)       RESET
XLXN_4              3       3       FB1_12  STD            (b)       (b)       RESET
XLXN_5              3       3       FB1_11  STD       6    GCK/I/O   (b)       RESET
XLXN_87             2       2       FB4_18  STD            (b)       (b)       RESET
XLXN_89             2       2       FB4_17  STD       34   I/O       (b)       RESET
XLXN_9              4       4       FB1_17  STD       9    I/O       (b)       RESET
a                   2       3       FB2_6   STD  SLOW 37   I/O       O         
b                   2       3       FB2_8   STD  SLOW 38   I/O       O         
c                   1       3       FB4_15  STD  SLOW 33   I/O       O         
d                   3       3       FB2_5   STD  SLOW 36   I/O       O         
e                   2       3       FB2_2   STD  SLOW 35   I/O       O         
f                   3       3       FB1_2   STD  SLOW 1    I/O       O         
g                   2       3       FB2_9   STD  SLOW 39   GSR/I/O   O         

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
S1                                  FB4_14            29   I/O       I
S3                                  FB4_8             27   I/O       I
SYNC                                FB1_9             5    GCK/I/O   GCK

End of Resources

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1          15          15          15           34         1/0        9   
FB2          13          15          15           18         6/0        9   
FB3           3          15          15            3         0/0        9   
FB4           4           7           7            6         1/0        7   
            ----                                -----       -----     ----- 
             35                                   61         8/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               15/39
Number of signals used by logic mapping into function block:  15
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB1_1               (b)     
f                     3       0     0   2     FB1_2   STD   1     I/O     O
(unused)              0       0     0   5     FB1_3               (b)     
(unused)              0       0     0   5     FB1_4               (b)     
XLXI_53/Q<5>          1       0     0   4     FB1_5   STD   2     I/O     (b)
XLXI_53/Q<4>          1       0     0   4     FB1_6   STD   3     I/O     (b)
XLXI_53/Q<3>          1       0     0   4     FB1_7   STD         (b)     (b)
XLXI_53/Q<2>          1       0     0   4     FB1_8   STD   4     I/O     (b)
XLXI_53/Q<1>          1       0     0   4     FB1_9   STD   5     GCK/I/O GCK
XLXI_53/Q<0>          0       0     0   5     FB1_10  STD         (b)     (b)
XLXN_5                3       0     0   2     FB1_11  STD   6     GCK/I/O (b)
XLXN_4                3       0     0   2     FB1_12  STD         (b)     (b)
XLXN_3                3       0     0   2     FB1_13  STD         (b)     (b)
XLXN_26               3       0     0   2     FB1_14  STD   7     GCK/I/O (b)
XLXN_24               3       0     0   2     FB1_15  STD   8     I/O     (b)
XLXN_1                3       0     0   2     FB1_16  STD         (b)     (b)
XLXN_9                4       0     0   1     FB1_17  STD   9     I/O     (b)
XLXN_28               4       0     0   1     FB1_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: S1                 6: XLXI_53/Q<4>      11: XLXN_3 
  2: XLXI_53/Q<0>       7: XLXN_1            12: XLXN_4 
  3: XLXI_53/Q<1>       8: XLXN_24           13: XLXN_5 
  4: XLXI_53/Q<2>       9: XLXN_26           14: XLXN_87 
  5: XLXI_53/Q<3>      10: XLXN_28           15: XLXN_9 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
f                    .......XX.X............................. 3       3
XLXI_53/Q<5>         .XXXXX.................................. 5       5
XLXI_53/Q<4>         .XXXX................................... 4       4
XLXI_53/Q<3>         .XXX.................................... 3       3
XLXI_53/Q<2>         .XX..................................... 2       2
XLXI_53/Q<1>         .X...................................... 1       1
XLXI_53/Q<0>         ........................................ 0       0
XLXN_5               X.....X......X.......................... 3       3
XLXN_4               X............XX......................... 3       3
XLXN_3               X..........X.X.......................... 3       3
XLXN_26              X......X.....X.......................... 3       3
XLXN_24              X.........X..X.......................... 3       3
XLXN_1               X.......X....X.......................... 3       3
XLXN_9               X........XX..X.......................... 4       4
XLXN_28              X.........X.XX.......................... 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               15/39
Number of signals used by logic mapping into function block:  15
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1               (b)     
e                     2       0     0   3     FB2_2   STD   35    I/O     O
(unused)              0       0     0   5     FB2_3               (b)     
(unused)              0       0     0   5     FB2_4               (b)     
d                     3       0     0   2     FB2_5   STD   36    I/O     O
a                     2       0     0   3     FB2_6   STD   37    I/O     O
(unused)              0       0     0   5     FB2_7               (b)     
b                     2       0     0   3     FB2_8   STD   38    I/O     O
g                     2       0     0   3     FB2_9   STD   39    GSR/I/O O
(unused)              0       0     0   5     FB2_10              (b)     
XLXI_53/Q<9>          1       0     0   4     FB2_11  STD   40    GTS/I/O (b)
XLXI_53/Q<8>          1       0     0   4     FB2_12  STD         (b)     (b)
XLXI_53/Q<7>          1       0     0   4     FB2_13  STD         (b)     (b)
T1                    0       0     0   5     FB2_14  STD   42    GTS/I/O O
XLXI_53/Q<6>          1       0     0   4     FB2_15  STD   43    I/O     (b)
XLXI_53/Q<12>         1       0     0   4     FB2_16  STD         (b)     (b)
XLXI_53/Q<11>         1       0     0   4     FB2_17  STD   44    I/O     (b)
XLXI_53/Q<10>         1       0     0   4     FB2_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: XLXI_53/Q<0>       6: XLXI_53/Q<3>      11: XLXI_53/Q<8> 
  2: XLXI_53/Q<10>      7: XLXI_53/Q<4>      12: XLXI_53/Q<9> 
  3: XLXI_53/Q<11>      8: XLXI_53/Q<5>      13: XLXN_24 
  4: XLXI_53/Q<1>       9: XLXI_53/Q<6>      14: XLXN_26 
  5: XLXI_53/Q<2>      10: XLXI_53/Q<7>      15: XLXN_3 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
e                    ............XXX......................... 3       3
d                    ............XXX......................... 3       3
a                    ............XXX......................... 3       3
b                    ............XXX......................... 3       3
g                    ............XXX......................... 3       3
XLXI_53/Q<9>         X..XXXXXXXX............................. 9       9
XLXI_53/Q<8>         X..XXXXXXX.............................. 8       8
XLXI_53/Q<7>         X..XXXXXX............................... 7       7
T1                   ........................................ 0       0
XLXI_53/Q<6>         X..XXXXX................................ 6       6
XLXI_53/Q<12>        XXXXXXXXXXXX............................ 12      12
XLXI_53/Q<11>        XX.XXXXXXXXX............................ 11      11
XLXI_53/Q<10>        X..XXXXXXXXX............................ 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               15/39
Number of signals used by logic mapping into function block:  15
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB3_1               (b)     
(unused)              0       0     0   5     FB3_2         11    I/O     
(unused)              0       0     0   5     FB3_3               (b)     
(unused)              0       0     0   5     FB3_4               (b)     
(unused)              0       0     0   5     FB3_5         12    I/O     
(unused)              0       0     0   5     FB3_6               (b)     
(unused)              0       0     0   5     FB3_7               (b)     
(unused)              0       0     0   5     FB3_8         13    I/O     
(unused)              0       0     0   5     FB3_9         14    I/O     
(unused)              0       0     0   5     FB3_10              (b)     
(unused)              0       0     0   5     FB3_11        18    I/O     
(unused)              0       0     0   5     FB3_12              (b)     
(unused)              0       0     0   5     FB3_13              (b)     
(unused)              0       0     0   5     FB3_14        19    I/O     
(unused)              0       0     0   5     FB3_15        20    I/O     
XLXI_53/Q<14>         1       0     0   4     FB3_16  STD   24    I/O     (b)
XLXI_53/Q<13>         1       0     0   4     FB3_17  STD   22    I/O     (b)
Q<15>                 1       0     0   4     FB3_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: XLXI_53/Q<0>       6: XLXI_53/Q<14>     11: XLXI_53/Q<5> 
  2: XLXI_53/Q<10>      7: XLXI_53/Q<1>      12: XLXI_53/Q<6> 
  3: XLXI_53/Q<11>      8: XLXI_53/Q<2>      13: XLXI_53/Q<7> 
  4: XLXI_53/Q<12>      9: XLXI_53/Q<3>      14: XLXI_53/Q<8> 
  5: XLXI_53/Q<13>     10: XLXI_53/Q<4>      15: XLXI_53/Q<9> 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
XLXI_53/Q<14>        XXXXX.XXXXXXXXX......................... 14      14
XLXI_53/Q<13>        XXXX..XXXXXXXXX......................... 13      13
Q<15>                XXXXXXXXXXXXXXX......................... 15      15
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               7/47
Number of signals used by logic mapping into function block:  7
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB4_1               (b)     
(unused)              0       0     0   5     FB4_2         25    I/O     
(unused)              0       0     0   5     FB4_3               (b)     
(unused)              0       0     0   5     FB4_4               (b)     
(unused)              0       0     0   5     FB4_5         26    I/O     
(unused)              0       0     0   5     FB4_6               (b)     
(unused)              0       0     0   5     FB4_7               (b)     
(unused)              0       0     0   5     FB4_8         27    I/O     I
(unused)              0       0     0   5     FB4_9               (b)     
(unused)              0       0     0   5     FB4_10              (b)     
(unused)              0       0     0   5     FB4_11        28    I/O     
(unused)              0       0     0   5     FB4_12              (b)     
(unused)              0       0     0   5     FB4_13              (b)     
(unused)              0       0     0   5     FB4_14        29    I/O     I
c                     1       0     0   4     FB4_15  STD   33    I/O     O
XLXI_57/Q0            1       0     0   4     FB4_16  STD         (b)     (b)
XLXN_89               2       0     0   3     FB4_17  STD   34    I/O     (b)
XLXN_87               2       0     0   3     FB4_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: Q<15>              4: XLXN_24            6: XLXN_3 
  2: S3                 5: XLXN_26            7: XLXN_89 
  3: XLXI_57/Q0       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
c                    ...XXX.................................. 3       3
XLXI_57/Q0           X....................................... 1       1
XLXN_89              X.X..................................... 2       2
XLXN_87              .X....X................................. 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

FTCPE_Q15: FTCPE port map (Q(15),Q_T(15),SYNC,'0','0');
Q_T(15) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND 
	XLXI_53/Q(12) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND 
	XLXI_53/Q(10) AND XLXI_53/Q(13) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND 
	XLXI_53/Q(11) AND XLXI_53/Q(14) AND XLXI_53/Q(3) AND XLXI_53/Q(7));


T1 <= '0';

FTCPE_XLXI_53/Q0: FTCPE port map (XLXI_53/Q(0),'1',SYNC,'0','0');

FTCPE_XLXI_53/Q10: FTCPE port map (XLXI_53/Q(10),XLXI_53/Q_T(10),SYNC,'0','0');
XLXI_53/Q_T(10) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND 
	XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND XLXI_53/Q(2) AND 
	XLXI_53/Q(6) AND XLXI_53/Q(3) AND XLXI_53/Q(7));

FTCPE_XLXI_53/Q11: FTCPE port map (XLXI_53/Q(11),XLXI_53/Q_T(11),SYNC,'0','0');
XLXI_53/Q_T(11) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND 
	XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND XLXI_53/Q(10) AND 
	XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(3) AND XLXI_53/Q(7));

FTCPE_XLXI_53/Q12: FTCPE port map (XLXI_53/Q(12),XLXI_53/Q_T(12),SYNC,'0','0');
XLXI_53/Q_T(12) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND 
	XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND XLXI_53/Q(10) AND 
	XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(11) AND XLXI_53/Q(3) AND 
	XLXI_53/Q(7));

FTCPE_XLXI_53/Q13: FTCPE port map (XLXI_53/Q(13),XLXI_53/Q_T(13),SYNC,'0','0');
XLXI_53/Q_T(13) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND 
	XLXI_53/Q(12) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND 
	XLXI_53/Q(10) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(11) AND 
	XLXI_53/Q(3) AND XLXI_53/Q(7));

FTCPE_XLXI_53/Q14: FTCPE port map (XLXI_53/Q(14),XLXI_53/Q_T(14),SYNC,'0','0');
XLXI_53/Q_T(14) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND 
	XLXI_53/Q(12) AND XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(9) AND 
	XLXI_53/Q(10) AND XLXI_53/Q(13) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND 
	XLXI_53/Q(11) AND XLXI_53/Q(3) AND XLXI_53/Q(7));

FTCPE_XLXI_53/Q1: FTCPE port map (XLXI_53/Q(1),XLXI_53/Q(0),SYNC,'0','0');

FTCPE_XLXI_53/Q2: FTCPE port map (XLXI_53/Q(2),XLXI_53/Q_T(2),SYNC,'0','0');
XLXI_53/Q_T(2) <= (XLXI_53/Q(0) AND XLXI_53/Q(1));

FTCPE_XLXI_53/Q3: FTCPE port map (XLXI_53/Q(3),XLXI_53/Q_T(3),SYNC,'0','0');
XLXI_53/Q_T(3) <= (XLXI_53/Q(0) AND XLXI_53/Q(1) AND XLXI_53/Q(2));

FTCPE_XLXI_53/Q4: FTCPE port map (XLXI_53/Q(4),XLXI_53/Q_T(4),SYNC,'0','0');
XLXI_53/Q_T(4) <= (XLXI_53/Q(0) AND XLXI_53/Q(1) AND XLXI_53/Q(2) AND 
	XLXI_53/Q(3));

FTCPE_XLXI_53/Q5: FTCPE port map (XLXI_53/Q(5),XLXI_53/Q_T(5),SYNC,'0','0');
XLXI_53/Q_T(5) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(1) AND 
	XLXI_53/Q(2) AND XLXI_53/Q(3));

FTCPE_XLXI_53/Q6: FTCPE port map (XLXI_53/Q(6),XLXI_53/Q_T(6),SYNC,'0','0');
XLXI_53/Q_T(6) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(1) AND 
	XLXI_53/Q(5) AND XLXI_53/Q(2) AND XLXI_53/Q(3));

FTCPE_XLXI_53/Q7: FTCPE port map (XLXI_53/Q(7),XLXI_53/Q_T(7),SYNC,'0','0');
XLXI_53/Q_T(7) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(1) AND 
	XLXI_53/Q(5) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(3));

FTCPE_XLXI_53/Q8: FTCPE port map (XLXI_53/Q(8),XLXI_53/Q_T(8),SYNC,'0','0');
XLXI_53/Q_T(8) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(1) AND 
	XLXI_53/Q(5) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND XLXI_53/Q(3) AND 
	XLXI_53/Q(7));

FTCPE_XLXI_53/Q9: FTCPE port map (XLXI_53/Q(9),XLXI_53/Q_T(9),SYNC,'0','0');
XLXI_53/Q_T(9) <= (XLXI_53/Q(0) AND XLXI_53/Q(4) AND XLXI_53/Q(8) AND 
	XLXI_53/Q(1) AND XLXI_53/Q(5) AND XLXI_53/Q(2) AND XLXI_53/Q(6) AND 
	XLXI_53/Q(3) AND XLXI_53/Q(7));

FTCPE_XLXI_57/Q0: FTCPE port map (XLXI_57/Q0,'1',Q(15),'0','0');

FDCPE_XLXN_1: FDCPE port map (XLXN_1,XLXN_26,NOT XLXN_87,NOT S1,'0');

FDCPE_XLXN_24: FDCPE port map (XLXN_24,NOT XLXN_3,NOT XLXN_87,NOT S1,'0');

FDCPE_XLXN_26: FDCPE port map (XLXN_26,XLXN_24,NOT XLXN_87,NOT S1,'0');

FDCPE_XLXN_28: FDCPE port map (XLXN_28,XLXN_28_D,NOT XLXN_87,NOT S1,'0');
XLXN_28_D <= XLXN_5
	 XOR 
XLXN_28_D <= XLXN_3;

FDCPE_XLXN_3: FDCPE port map (XLXN_3,XLXN_4,NOT XLXN_87,NOT S1,'0');

FDCPE_XLXN_4: FDCPE port map (XLXN_4,XLXN_9,NOT XLXN_87,NOT S1,'0');

FDCPE_XLXN_5: FDCPE port map (XLXN_5,XLXN_1,NOT XLXN_87,NOT S1,'0');

FDCPE_XLXN_87: FDCPE port map (XLXN_87,S3,XLXN_89,'0','0');

FTCPE_XLXN_89: FTCPE port map (XLXN_89,XLXI_57/Q0,Q(15),'0','0');

FDCPE_XLXN_9: FDCPE port map (XLXN_9,XLXN_9_D,NOT XLXN_87,NOT S1,'0');
XLXN_9_D <= XLXN_3
	 XOR 
XLXN_9_D <= XLXN_28;


a <= ((NOT XLXN_24 AND XLXN_26 AND XLXN_3)
	OR (NOT XLXN_24 AND NOT XLXN_26 AND NOT XLXN_3));


b <= ((XLXN_24 AND XLXN_26 AND XLXN_3)
	OR (NOT XLXN_24 AND XLXN_26 AND NOT XLXN_3));


c <= (XLXN_24 AND NOT XLXN_26 AND XLXN_3);


d <= ((XLXN_24 AND XLXN_26 AND NOT XLXN_3)
	OR (NOT XLXN_24 AND XLXN_26 AND XLXN_3)
	OR (NOT XLXN_24 AND NOT XLXN_26 AND NOT XLXN_3));


e <= ((NOT XLXN_3)
	OR (NOT XLXN_24 AND XLXN_26));


f <= NOT (((NOT XLXN_24 AND XLXN_26)
	OR (NOT XLXN_24 AND XLXN_3)
	OR (XLXN_26 AND XLXN_3)));


g <= ((NOT XLXN_24 AND NOT XLXN_26)
	OR (XLXN_24 AND XLXN_26 AND NOT XLXN_3));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

****************************  Device Pin Out ****************************

Device : XC9572XL-10-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XC9572XL-10-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 f                                23 GND                           
  2 TIE                              24 TIE                           
  3 TIE                              25 TIE                           
  4 TIE                              26 TIE                           
  5 SYNC                             27 S3                            
  6 TIE                              28 TIE                           
  7 TIE                              29 S1                            
  8 TIE                              30 TDO                           
  9 TIE                              31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 c                             
 12 TIE                              34 TIE                           
 13 TIE                              35 e                             
 14 TIE                              36 d                             
 15 TDI                              37 a                             
 16 TMS                              38 b                             
 17 TCK                              39 g                             
 18 TIE                              40 TIE                           
 19 TIE                              41 VCC                           
 20 TIE                              42 T1                            
 21 VCC                              43 TIE                           
 22 TIE                              44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : STD
Set Unused I/O Pin Termination              : FLOAT
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25