cpldfit:  version G.28                              Xilinx Inc.
                                  Fitter Report
Design Name: kostka_anim                         Date: 10-22-2008,  4:35PM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
18 /72  ( 25%) 71  /360  ( 20%) 8  /72  ( 11%) 13 /34  ( 38%) 34 /216 ( 16%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    4           4    |  I/O              :     9       19
Output        :    8           8    |  GCK/IO           :     2        1
Bidirectional :    0           0    |  GTS/IO           :     1        1
GCK           :    1           1    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     13          13

MACROCELL RESOURCES:

Total Macrocells Available                    72
Registered Macrocells                          8
Non-registered Macrocell driving I/O           8

GLOBAL RESOURCES:

Signal 'SYNC' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 18 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 18 macrocells used (MC).

End of Resource Summary
*************** Summary of Required Resources ******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin       Reg Init
Name                Pt      Used            Mode Rate #    Type      Use       State
T1                  0       0       FB2_14  STD  SLOW 42   GTS/I/O   O         
XLXN_13             3       5       FB4_18  STD            (b)       (b)       RESET
XLXN_14             3       4       FB4_17  STD       34   I/O       (b)       RESET
XLXN_145            2       3       FB1_15  STD       8    I/O       (b)       RESET
XLXN_146            3       4       FB1_18  STD            (b)       (b)       RESET
XLXN_147            3       4       FB1_17  STD       9    I/O       (b)       RESET
XLXN_15             3       3       FB4_16  STD            (b)       (b)       RESET
XLXN_15/XLXN_15_RSTF                    3       6       FB1_16  STD            (b)       (b)       
XLXN_151            1       1       FB3_18  STD            (b)       (b)       RESET
XLXN_16             2       2       FB4_14  STD       29   I/O       I         RESET
XLXN_16/XLXN_16_CLKF__$INT                    2       4       FB2_18  STD            (b)       (b)       
segA                7       10      FB2_6   STD  SLOW 37   I/O       O         
segB                6       9       FB2_8   STD  SLOW 38   I/O       O         
segC                6       9       FB4_15  STD  SLOW 33   I/O       O         
segD                8       10      FB2_5   STD  SLOW 36   I/O       O         
segE                5       9       FB2_2   STD  SLOW 35   I/O       O         
segF                7       10      FB1_2   STD  SLOW 1    I/O       O         
segG                7       10      FB2_9   STD  SLOW 39   GSR/I/O   O         

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
CLK                                 FB1_14            7    GCK/I/O   I
S1                                  FB4_14            29   I/O       I
S2                                  FB4_11            28   I/O       I
S3                                  FB4_8             27   I/O       I
SYNC                                FB1_9             5    GCK/I/O   GCK/I

End of Resources

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           5          11          11           18         1/0        9   
FB2           7          11          11           35         6/0        9   
FB3           1           1           1            1         0/0        9   
FB4           5          11          11           17         1/0        7   
            ----                                -----       -----     ----- 
             18                                   71         8/0       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               11/43
Number of signals used by logic mapping into function block:  11
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0   \/1   4     FB1_1               (b)     (b)
segF                  7       2<-   0   0     FB1_2   STD   1     I/O     O
(unused)              0       0   /\1   4     FB1_3               (b)     (b)
(unused)              0       0     0   5     FB1_4               (b)     
(unused)              0       0     0   5     FB1_5         2     I/O     
(unused)              0       0     0   5     FB1_6         3     I/O     
(unused)              0       0     0   5     FB1_7               (b)     
(unused)              0       0     0   5     FB1_8         4     I/O     
(unused)              0       0     0   5     FB1_9         5     GCK/I/O GCK/I
(unused)              0       0     0   5     FB1_10              (b)     
(unused)              0       0     0   5     FB1_11        6     GCK/I/O 
(unused)              0       0     0   5     FB1_12              (b)     
(unused)              0       0     0   5     FB1_13              (b)     
(unused)              0       0     0   5     FB1_14        7     GCK/I/O I
XLXN_145              2       0     0   3     FB1_15  STD   8     I/O     (b)
XLXN_15/XLXN_15_RSTF
                      3       0     0   2     FB1_16  STD         (b)     (b)
XLXN_147              3       0     0   2     FB1_17  STD   9     I/O     (b)
XLXN_146              3       0     0   2     FB1_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: S1                 5: XLXN_14            9: XLXN_15 
  2: S2                 6: XLXN_145          10: XLXN_151 
  3: S3                 7: XLXN_146          11: XLXN_16 
  4: XLXN_13            8: XLXN_147         

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
segF                 XXXXXXXXX.X............................. 10      10
XLXN_145             ......XX.X.............................. 3       3
XLXN_15/XLXN_15_RSTF 
                     XXXXX...X............................... 6       6
XLXN_147             .....XXX.X.............................. 4       4
XLXN_146             .....XXX.X.............................. 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               11/43
Number of signals used by logic mapping into function block:  11
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1               (b)     
segE                  5       0     0   0     FB2_2   STD   35    I/O     O
(unused)              0       0     0   5     FB2_3               (b)     
(unused)              0       0   \/3   2     FB2_4               (b)     (b)
segD                  8       3<-   0   0     FB2_5   STD   36    I/O     O
segA                  7       2<-   0   0     FB2_6   STD   37    I/O     O
(unused)              0       0   /\2   3     FB2_7               (b)     (b)
segB                  6       1<-   0   0     FB2_8   STD   38    I/O     O
segG                  7       3<- /\1   0     FB2_9   STD   39    GSR/I/O O
(unused)              0       0   /\3   2     FB2_10              (b)     (b)
(unused)              0       0     0   5     FB2_11        40    GTS/I/O 
(unused)              0       0     0   5     FB2_12              (b)     
(unused)              0       0     0   5     FB2_13              (b)     
T1                    0       0     0   5     FB2_14  STD   42    GTS/I/O O
(unused)              0       0     0   5     FB2_15        43    I/O     
(unused)              0       0     0   5     FB2_16              (b)     
(unused)              0       0     0   5     FB2_17        44    I/O     
XLXN_16/XLXN_16_CLKF__$INT
                      2       0     0   3     FB2_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: S1                 5: XLXN_13            9: XLXN_147 
  2: S2                 6: XLXN_14           10: XLXN_15 
  3: S3                 7: XLXN_145          11: XLXN_16 
  4: SYNC               8: XLXN_146         

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
segE                 XXX..XXXXXX............................. 9       9
segD                 XXX.XXXXXXX............................. 10      10
segA                 XXX.XXXXXXX............................. 10      10
segB                 XXX..XXXXXX............................. 9       9
segG                 XXX.XXXXXXX............................. 10      10
T1                   ........................................ 0       0
XLXN_16/XLXN_16_CLKF__$INT 
                     XXXX.................................... 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               1/53
Number of signals used by logic mapping into function block:  1
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB3_1               (b)     
(unused)              0       0     0   5     FB3_2         11    I/O     
(unused)              0       0     0   5     FB3_3               (b)     
(unused)              0       0     0   5     FB3_4               (b)     
(unused)              0       0     0   5     FB3_5         12    I/O     
(unused)              0       0     0   5     FB3_6               (b)     
(unused)              0       0     0   5     FB3_7               (b)     
(unused)              0       0     0   5     FB3_8         13    I/O     
(unused)              0       0     0   5     FB3_9         14    I/O     
(unused)              0       0     0   5     FB3_10              (b)     
(unused)              0       0     0   5     FB3_11        18    I/O     
(unused)              0       0     0   5     FB3_12              (b)     
(unused)              0       0     0   5     FB3_13              (b)     
(unused)              0       0     0   5     FB3_14        19    I/O     
(unused)              0       0     0   5     FB3_15        20    I/O     
(unused)              0       0     0   5     FB3_16        24    I/O     
(unused)              0       0     0   5     FB3_17        22    I/O     
XLXN_151              1       0     0   4     FB3_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: CLK              

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
XLXN_151             X....................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               11/43
Number of signals used by logic mapping into function block:  11
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB4_1               (b)     
(unused)              0       0     0   5     FB4_2         25    I/O     
(unused)              0       0     0   5     FB4_3               (b)     
(unused)              0       0     0   5     FB4_4               (b)     
(unused)              0       0     0   5     FB4_5         26    I/O     
(unused)              0       0     0   5     FB4_6               (b)     
(unused)              0       0     0   5     FB4_7               (b)     
(unused)              0       0     0   5     FB4_8         27    I/O     I
(unused)              0       0     0   5     FB4_9               (b)     
(unused)              0       0     0   5     FB4_10              (b)     
(unused)              0       0     0   5     FB4_11        28    I/O     I
(unused)              0       0     0   5     FB4_12              (b)     
(unused)              0       0     0   5     FB4_13              (b)     
XLXN_16               2       0   \/1   2     FB4_14  STD   29    I/O     I
segC                  6       1<-   0   0     FB4_15  STD   33    I/O     O
XLXN_15               3       0     0   2     FB4_16  STD         (b)     (b)
XLXN_14               3       0     0   2     FB4_17  STD   34    I/O     (b)
XLXN_13               3       0     0   2     FB4_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: S1                 5: XLXN_145           9: XLXN_15/XLXN_15_RSTF 
  2: S2                 6: XLXN_146          10: XLXN_16 
  3: S3                 7: XLXN_147          11: XLXN_16/XLXN_16_CLKF__$INT 
  4: XLXN_14            8: XLXN_15          

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
XLXN_16              ........X.X............................. 2       2
segC                 XXXXXXXX.X.............................. 9       9
XLXN_15              ........XXX............................. 3       3
XLXN_14              .......XXXX............................. 4       4
XLXN_13              ...X...XXXX............................. 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.












T1 <= '0';

FTCPE_XLXN_13: FTCPE port map (XLXN_13,XLXN_13_T,NOT XLXN_16/XLXN_16_CLKF__$INT,XLXN_15/XLXN_15_RSTF,'0');
XLXN_13_T <= (XLXN_15 AND XLXN_14 AND XLXN_16);

FTCPE_XLXN_14: FTCPE port map (XLXN_14,XLXN_14_T,NOT XLXN_16/XLXN_16_CLKF__$INT,XLXN_15/XLXN_15_RSTF,'0');
XLXN_14_T <= (XLXN_15 AND XLXN_16);

FTCPE_XLXN_145: FTCPE port map (XLXN_145,'1',XLXN_151,XLXN_145_CLR,'0');
XLXN_145_CLR <= (XLXN_146 AND XLXN_147);

FTCPE_XLXN_146: FTCPE port map (XLXN_146,XLXN_145,XLXN_151,XLXN_146_CLR,'0');
XLXN_146_CLR <= (XLXN_146 AND XLXN_147);

FTCPE_XLXN_147: FTCPE port map (XLXN_147,XLXN_147_T,XLXN_151,XLXN_147_CLR,'0');
XLXN_147_T <= (XLXN_145 AND XLXN_146);
XLXN_147_CLR <= (XLXN_146 AND XLXN_147);

FTCPE_XLXN_15: FTCPE port map (XLXN_15,XLXN_16,NOT XLXN_16/XLXN_16_CLKF__$INT,XLXN_15/XLXN_15_RSTF,'0');


XLXN_15/XLXN_15_RSTF <= ((XLXN_14 AND NOT S1)
	OR (XLXN_15 AND XLXN_14 AND NOT S2)
	OR (XLXN_15 AND NOT S3 AND XLXN_13));

FDCPE_XLXN_151: FDCPE port map (XLXN_151,CLK,SYNC,'0','0');

FTCPE_XLXN_16: FTCPE port map (XLXN_16,'1',NOT XLXN_16/XLXN_16_CLKF__$INT,XLXN_15/XLXN_15_RSTF,'0');


XLXN_16/XLXN_16_CLKF__$INT <= ((NOT SYNC)
	OR (S3 AND S2 AND S1));


segA <= NOT (((EXP9_.EXP)
	OR (XLXN_15 AND S3 AND S2 AND S1)
	OR (NOT S3 AND NOT XLXN_145 AND NOT XLXN_146 AND NOT XLXN_147)
	OR (NOT S2 AND NOT XLXN_145 AND NOT XLXN_146 AND NOT XLXN_147)
	OR (NOT S1 AND NOT XLXN_145 AND NOT XLXN_146 AND NOT XLXN_147)
	OR (XLXN_16 AND S3 AND S2 AND S1 AND XLXN_13)));


segB <= NOT (((segG_OBUF.EXP)
	OR (NOT XLXN_14 AND S3 AND S2 AND S1)
	OR (NOT S3 AND XLXN_145 AND NOT XLXN_146 AND NOT XLXN_147)
	OR (NOT S2 AND XLXN_145 AND NOT XLXN_146 AND NOT XLXN_147)
	OR (NOT S1 AND XLXN_145 AND NOT XLXN_146 AND NOT XLXN_147)
	OR (XLXN_15 AND XLXN_16 AND S3 AND S2 AND S1)));


segC <= NOT (((XLXN_16.EXP)
	OR (NOT XLXN_15 AND S3 AND S2 AND S1)
	OR (XLXN_14 AND S3 AND S2 AND S1)
	OR (NOT S3 AND NOT XLXN_145 AND XLXN_146 AND NOT XLXN_147)
	OR (NOT S2 AND NOT XLXN_145 AND XLXN_146 AND NOT XLXN_147)
	OR (NOT S1 AND NOT XLXN_145 AND XLXN_146 AND NOT XLXN_147)));


segD <= NOT (((EXP8_.EXP)
	OR (NOT S3 AND XLXN_145 AND XLXN_146 AND NOT XLXN_147)
	OR (NOT S2 AND XLXN_145 AND XLXN_146 AND NOT XLXN_147)
	OR (NOT S1 AND XLXN_145 AND XLXN_146 AND NOT XLXN_147)
	OR (XLXN_15 AND NOT XLXN_14 AND S3 AND S2 AND S1)
	OR (XLXN_15 AND NOT XLXN_16 AND S3 AND S2 AND S1)));


segE <= NOT (((NOT S3 AND NOT XLXN_145 AND NOT XLXN_146 AND XLXN_147)
	OR (NOT S2 AND NOT XLXN_145 AND NOT XLXN_146 AND XLXN_147)
	OR (NOT S1 AND NOT XLXN_145 AND NOT XLXN_146 AND XLXN_147)
	OR (XLXN_15 AND NOT XLXN_16 AND S3 AND S2 AND S1)
	OR (NOT XLXN_14 AND NOT XLXN_16 AND S3 AND S2 AND S1)));


segF <= NOT (((EXP6_.EXP)
	OR (EXP7_.EXP)
	OR (NOT S3 AND XLXN_145 AND NOT XLXN_146 AND XLXN_147)
	OR (NOT S2 AND XLXN_145 AND NOT XLXN_146 AND XLXN_147)
	OR (NOT S1 AND XLXN_145 AND NOT XLXN_146 AND XLXN_147)
	OR (NOT XLXN_15 AND XLXN_14 AND S3 AND S2 AND S1)
	OR (XLXN_14 AND NOT XLXN_16 AND S3 AND S2 AND S1)));


segG <= NOT (((EXP10_.EXP)
	OR (NOT S3 AND NOT XLXN_145 AND XLXN_146 AND XLXN_147)
	OR (NOT S2 AND NOT XLXN_145 AND XLXN_146 AND XLXN_147)
	OR (XLXN_14 AND NOT XLXN_16 AND S3 AND S2 AND S1)
	OR (NOT XLXN_14 AND S3 AND S2 AND S1 AND XLXN_13)));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

****************************  Device Pin Out ****************************

Device : XC9572XL-10-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XC9572XL-10-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 segF                             23 GND                           
  2 TIE                              24 TIE                           
  3 TIE                              25 TIE                           
  4 TIE                              26 TIE                           
  5 SYNC                             27 S3                            
  6 TIE                              28 S2                            
  7 CLK                              29 S1                            
  8 TIE                              30 TDO                           
  9 TIE                              31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 segC                          
 12 TIE                              34 TIE                           
 13 TIE                              35 segE                          
 14 TIE                              36 segD                          
 15 TDI                              37 segA                          
 16 TMS                              38 segB                          
 17 TCK                              39 segG                          
 18 TIE                              40 TIE                           
 19 TIE                              41 VCC                           
 20 TIE                              42 T1                            
 21 VCC                              43 TIE                           
 22 TIE                              44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : STD
Set Unused I/O Pin Termination              : FLOAT
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25