cpldfit: version G.28 Xilinx Inc. Fitter Report Design Name: lfsr Date: 10-25-2008, 6:32PM Device Used: XC9572XL-10-PC44 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 16 /72 ( 22%) 41 /360 ( 11%) 8 /72 ( 11%) 10 /34 ( 29%) 18 /216 ( 8%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 2 2 | I/O : 8 20 Output : 8 8 | GCK/IO : 0 3 Bidirectional : 0 0 | GTS/IO : 1 1 GCK : 0 0 | GSR/IO : 1 0 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 10 10 MACROCELL RESOURCES: Total Macrocells Available 72 Registered Macrocells 8 Non-registered Macrocell driving I/O 8 GLOBAL RESOURCES: Global clock net(s) unused. Global output enable net(s) unused. Global set/reset net(s) unused. POWER DATA: There are 16 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 16 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State T1 0 0 FB2_14 STD SLOW 42 GTS/I/O O XLXN_1 3 3 FB1_16 STD (b) (b) RESET XLXN_10 4 4 FB1_18 STD (b) (b) RESET XLXN_12 4 4 FB1_17 STD 9 I/O (b) RESET XLXN_21 3 3 FB1_15 STD 8 I/O (b) RESET XLXN_3 3 3 FB1_14 STD 7 GCK/I/O (b) RESET XLXN_6 3 3 FB1_13 STD (b) (b) RESET XLXN_7 3 3 FB2_18 STD (b) (b) RESET XLXN_8 3 3 FB2_17 STD 44 I/O (b) RESET a 2 3 FB2_6 STD SLOW 37 I/O O b 2 3 FB2_8 STD SLOW 38 I/O O c 1 3 FB4_15 STD SLOW 33 I/O O d 3 3 FB2_5 STD SLOW 36 I/O O e 2 3 FB2_2 STD SLOW 35 I/O O f 3 3 FB1_2 STD SLOW 1 I/O O g 2 3 FB2_9 STD SLOW 39 GSR/I/O O ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use S1 FB4_14 29 I/O I S3 FB4_8 27 I/O I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 7 8 8 23 1/0 9 FB2 8 7 7 17 6/0 9 FB3 0 0 0 0 0/0 9 FB4 1 3 3 1 1/0 7 ---- ----- ----- ----- 16 41 8/0 34 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 8/46 Number of signals used by logic mapping into function block: 8 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB1_1 (b) f 3 0 0 2 FB1_2 STD 1 I/O O (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 2 I/O (unused) 0 0 0 5 FB1_6 3 I/O (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 4 I/O (unused) 0 0 0 5 FB1_9 5 GCK/I/O (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 6 GCK/I/O (unused) 0 0 0 5 FB1_12 (b) XLXN_6 3 0 0 2 FB1_13 STD (b) (b) XLXN_3 3 0 0 2 FB1_14 STD 7 GCK/I/O (b) XLXN_21 3 0 0 2 FB1_15 STD 8 I/O (b) XLXN_1 3 0 0 2 FB1_16 STD (b) (b) XLXN_12 4 0 0 1 FB1_17 STD 9 I/O (b) XLXN_10 4 0 0 1 FB1_18 STD (b) (b) Signals Used by Logic in Function Block 1: S1 4: XLXN_10 7: XLXN_7 2: S3 5: XLXN_21 8: XLXN_8 3: XLXN_1 6: XLXN_6 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs f ..X.XX.................................. 3 3 XLXN_6 XX....X................................. 3 3 XLXN_3 XX..X................................... 3 3 XLXN_21 XXX..................................... 3 3 XLXN_1 XX...X.................................. 3 3 XLXN_12 XX.X.X.................................. 4 4 XLXN_10 XX...X.X................................ 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 7/47 Number of signals used by logic mapping into function block: 7 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB2_1 (b) e 2 0 0 3 FB2_2 STD 35 I/O O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) d 3 0 0 2 FB2_5 STD 36 I/O O a 2 0 0 3 FB2_6 STD 37 I/O O (unused) 0 0 0 5 FB2_7 (b) b 2 0 0 3 FB2_8 STD 38 I/O O g 2 0 0 3 FB2_9 STD 39 GSR/I/O O (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 40 GTS/I/O (unused) 0 0 0 5 FB2_12 (b) (unused) 0 0 0 5 FB2_13 (b) T1 0 0 0 5 FB2_14 STD 42 GTS/I/O O (unused) 0 0 0 5 FB2_15 43 I/O (unused) 0 0 0 5 FB2_16 (b) XLXN_8 3 0 0 2 FB2_17 STD 44 I/O (b) XLXN_7 3 0 0 2 FB2_18 STD (b) (b) Signals Used by Logic in Function Block 1: S1 4: XLXN_12 6: XLXN_3 2: S3 5: XLXN_21 7: XLXN_6 3: XLXN_1 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs e ..X.X.X................................. 3 3 d ..X.X.X................................. 3 3 a ..X.X.X................................. 3 3 b ..X.X.X................................. 3 3 g ..X.X.X................................. 3 3 T1 ........................................ 0 0 XLXN_8 XX...X.................................. 3 3 XLXN_7 XX.X.................................... 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 11 I/O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 12 I/O (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 13 I/O (unused) 0 0 0 5 FB3_9 14 I/O (unused) 0 0 0 5 FB3_10 (b) (unused) 0 0 0 5 FB3_11 18 I/O (unused) 0 0 0 5 FB3_12 (b) (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 19 I/O (unused) 0 0 0 5 FB3_15 20 I/O (unused) 0 0 0 5 FB3_16 24 I/O (unused) 0 0 0 5 FB3_17 22 I/O (unused) 0 0 0 5 FB3_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 3/51 Number of signals used by logic mapping into function block: 3 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 25 I/O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 26 I/O (unused) 0 0 0 5 FB4_6 (b) (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 27 I/O I (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 28 I/O (unused) 0 0 0 5 FB4_12 (b) (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 29 I/O I c 1 0 0 4 FB4_15 STD 33 I/O O (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 34 I/O (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: XLXN_1 2: XLXN_21 3: XLXN_6 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs c XXX..................................... 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. T1 <= '0'; FDCPE_XLXN_1: FDCPE port map (XLXN_1,NOT XLXN_6,NOT S3,NOT S1,'0'); FDCPE_XLXN_10: FDCPE port map (XLXN_10,XLXN_10_D,NOT S3,NOT S1,'0'); XLXN_10_D <= XLXN_8 XOR XLXN_10_D <= XLXN_6; FDCPE_XLXN_12: FDCPE port map (XLXN_12,XLXN_12_D,NOT S3,NOT S1,'0'); XLXN_12_D <= XLXN_6 XOR XLXN_12_D <= XLXN_10; FDCPE_XLXN_21: FDCPE port map (XLXN_21,XLXN_1,NOT S3,NOT S1,'0'); FDCPE_XLXN_3: FDCPE port map (XLXN_3,XLXN_21,NOT S3,NOT S1,'0'); FDCPE_XLXN_6: FDCPE port map (XLXN_6,XLXN_7,NOT S3,NOT S1,'0'); FDCPE_XLXN_7: FDCPE port map (XLXN_7,XLXN_12,NOT S3,NOT S1,'0'); FDCPE_XLXN_8: FDCPE port map (XLXN_8,XLXN_3,NOT S3,NOT S1,'0'); a <= ((NOT XLXN_1 AND XLXN_21 AND XLXN_6) OR (NOT XLXN_1 AND NOT XLXN_21 AND NOT XLXN_6)); b <= ((XLXN_1 AND XLXN_21 AND XLXN_6) OR (NOT XLXN_1 AND XLXN_21 AND NOT XLXN_6)); c <= (XLXN_1 AND NOT XLXN_21 AND XLXN_6); d <= ((XLXN_1 AND XLXN_21 AND NOT XLXN_6) OR (NOT XLXN_1 AND XLXN_21 AND XLXN_6) OR (NOT XLXN_1 AND NOT XLXN_21 AND NOT XLXN_6)); e <= ((NOT XLXN_6) OR (NOT XLXN_1 AND XLXN_21)); f <= NOT (((NOT XLXN_1 AND XLXN_21) OR (NOT XLXN_1 AND XLXN_6) OR (XLXN_21 AND XLXN_6))); g <= ((NOT XLXN_1 AND NOT XLXN_21) OR (XLXN_1 AND XLXN_21 AND NOT XLXN_6)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); **************************** Device Pin Out **************************** Device : XC9572XL-10-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572XL-10-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 f 23 GND 2 TIE 24 TIE 3 TIE 25 TIE 4 TIE 26 TIE 5 TIE 27 S3 6 TIE 28 TIE 7 TIE 29 S1 8 TIE 30 TDO 9 TIE 31 GND 10 GND 32 VCC 11 TIE 33 c 12 TIE 34 TIE 13 TIE 35 e 14 TIE 36 d 15 TDI 37 a 16 TMS 38 b 17 TCK 39 g 18 TIE 40 TIE 19 TIE 41 VCC 20 TIE 42 T1 21 VCC 43 TIE 22 TIE 44 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : SLOW Power Mode : STD Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25