cpldfit: version G.28 Xilinx Inc. Fitter Report Design Name: test_pcb Date: 6-14-2008, 1:33PM Device Used: XC9572XL-10-PC44 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 46 /72 ( 64%) 81 /360 ( 22%) 30 /72 ( 42%) 25 /34 ( 74%) 48 /216 ( 22%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 4 4 | I/O : 20 8 Output : 18 18 | GCK/IO : 3 0 Bidirectional : 0 0 | GTS/IO : 1 1 GCK : 3 3 | GSR/IO : 1 0 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 25 25 MACROCELL RESOURCES: Total Macrocells Available 72 Registered Macrocells 30 Non-registered Macrocell driving I/O 16 GLOBAL RESOURCES: Signal 'CLK_GEN' mapped onto global clock net GCK1. Signal 'CLK_FR' mapped onto global clock net GCK2. Signal 'CLK' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. POWER DATA: There are 46 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 46 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State IRED_OUT 1 2 FB3_14 STD FAST 19 I/O O LED1 2 4 FB3_11 STD FAST 18 I/O O LED2 2 4 FB3_15 STD FAST 20 I/O O LED3 2 4 FB3_17 STD FAST 22 I/O O LED4 2 4 FB3_16 STD FAST 24 I/O O LED5 2 4 FB4_5 STD FAST 26 I/O O MOSFET 1 1 FB1_8 STD FAST 4 I/O O REL 1 1 FB1_5 STD FAST 2 I/O O T1 1 3 FB2_17 STD FAST 44 I/O O RESET T2 2 4 FB2_14 STD FAST 42 GTS/I/O O SET XLXI_125/Q0 1 1 FB1_15 STD 8 I/O (b) RESET XLXI_125/Q1 2 2 FB1_18 STD (b) (b) RESET XLXI_125/Q2 2 3 FB1_17 STD 9 I/O I RESET XLXI_34/Q0 0 0 FB2_12 STD (b) (b) RESET XLXI_34/Q1 1 1 FB2_11 STD 40 GTS/I/O (b) RESET XLXI_34/Q2 1 2 FB2_10 STD (b) (b) RESET XLXI_91/Q0 0 0 FB2_7 STD (b) (b) RESET XLXI_91/Q1 1 1 FB2_4 STD (b) (b) RESET XLXI_91/Q2 1 2 FB2_3 STD (b) (b) RESET XLXI_92/Q0 2 3 FB4_12 STD (b) (b) RESET XLXI_92/Q2 3 4 FB4_18 STD (b) (b) RESET XLXI_93/Q0 1 1 FB4_10 STD (b) (b) RESET XLXI_93/Q2 2 3 FB3_13 STD (b) (b) RESET XLXN_103 3 4 FB4_16 STD (b) (b) RESET XLXN_113 0 0 FB1_14 STD 7 GCK/I/O GCK RESET XLXN_13 2 3 FB2_13 STD (b) (b) RESET XLXN_139 3 5 FB3_18 STD (b) (b) RESET XLXN_140 3 4 FB4_14 STD 29 I/O I RESET XLXN_144 1 3 FB2_1 STD (b) (b) RESET XLXN_16 3 5 FB2_18 STD (b) (b) RESET XLXN_186 2 2 FB3_12 STD (b) (b) RESET XLXN_197 2 4 FB1_16 STD (b) (b) RESET XLXN_198 2 4 FB3_10 STD (b) (b) RESET XLXN_386 3 3 FB4_13 STD (b) (b) RESET XLXN_388 2 3 FB4_11 STD 28 I/O I RESET XLXN_43 3 4 FB2_16 STD (b) (b) RESET XLXN_44 3 4 FB2_15 STD 43 I/O (b) RESET XLXN_46 0 0 FB1_13 STD (b) (b) RESET a 2 4 FB2_6 STD FAST 37 I/O O b 2 3 FB2_8 STD FAST 38 I/O O c 1 3 FB4_15 STD FAST 33 I/O O d 3 4 FB2_5 STD FAST 36 I/O O dp 1 1 FB4_17 STD FAST 34 I/O O e 2 3 FB2_2 STD FAST 35 I/O O f 3 4 FB1_2 STD FAST 1 I/O O g 2 4 FB2_9 STD FAST 39 GSR/I/O O ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use CLK FB1_14 7 GCK/I/O GCK CLK_FR FB1_11 6 GCK/I/O GCK CLK_GEN FB1_9 5 GCK/I/O GCK S1 FB4_14 29 I/O I S2 FB4_11 28 I/O I S3 FB4_8 27 I/O I SFH FB1_17 9 I/O I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 9 10 10 12 3/0 9 FB2 18 12 12 30 7/0 9 FB3 9 13 13 18 5/0 9 FB4 10 13 13 21 3/0 7 ---- ----- ----- ----- 46 81 18/0 34 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 10/44 Number of signals used by logic mapping into function block: 10 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB1_1 (b) f 3 0 0 2 FB1_2 STD 1 I/O O (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) REL 1 0 0 4 FB1_5 STD 2 I/O O (unused) 0 0 0 5 FB1_6 3 I/O (unused) 0 0 0 5 FB1_7 (b) MOSFET 1 0 0 4 FB1_8 STD 4 I/O O (unused) 0 0 0 5 FB1_9 5 GCK/I/O GCK (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 6 GCK/I/O GCK (unused) 0 0 0 5 FB1_12 (b) XLXN_46 0 0 0 5 FB1_13 STD (b) (b) XLXN_113 0 0 0 5 FB1_14 STD 7 GCK/I/O GCK XLXI_125/Q0 1 0 0 4 FB1_15 STD 8 I/O (b) XLXN_197 2 0 0 3 FB1_16 STD (b) (b) XLXI_125/Q2 2 0 0 3 FB1_17 STD 9 I/O I XLXI_125/Q1 2 0 0 3 FB1_18 STD (b) (b) Signals Used by Logic in Function Block 1: S2 5: XLXI_125/Q2 8: XLXN_198 2: S3 6: XLXN_13 9: XLXN_43 3: XLXI_125/Q0 7: XLXN_16 10: XLXN_44 4: XLXI_125/Q1 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs f .....XX.XX.............................. 4 4 REL .X...................................... 1 1 MOSFET X....................................... 1 1 XLXN_46 ........................................ 0 0 XLXN_113 ........................................ 0 0 XLXI_125/Q0 .......X................................ 1 1 XLXN_197 ..XXX..X................................ 4 4 XLXI_125/Q2 ..XX...X................................ 3 3 XLXI_125/Q1 ..X....X................................ 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 12/42 Number of signals used by logic mapping into function block: 12 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use XLXN_144 1 0 0 4 FB2_1 STD (b) (b) e 2 0 0 3 FB2_2 STD 35 I/O O XLXI_91/Q2 1 0 0 4 FB2_3 STD (b) (b) XLXI_91/Q1 1 0 0 4 FB2_4 STD (b) (b) d 3 0 0 2 FB2_5 STD 36 I/O O a 2 0 0 3 FB2_6 STD 37 I/O O XLXI_91/Q0 0 0 0 5 FB2_7 STD (b) (b) b 2 0 0 3 FB2_8 STD 38 I/O O g 2 0 0 3 FB2_9 STD 39 GSR/I/O O XLXI_34/Q2 1 0 0 4 FB2_10 STD (b) (b) XLXI_34/Q1 1 0 0 4 FB2_11 STD 40 GTS/I/O (b) XLXI_34/Q0 0 0 0 5 FB2_12 STD (b) (b) XLXN_13 2 0 0 3 FB2_13 STD (b) (b) T2 2 0 0 3 FB2_14 STD 42 GTS/I/O O XLXN_44 3 0 0 2 FB2_15 STD 43 I/O (b) XLXN_43 3 0 0 2 FB2_16 STD (b) (b) T1 1 0 0 4 FB2_17 STD 44 I/O O XLXN_16 3 0 0 2 FB2_18 STD (b) (b) Signals Used by Logic in Function Block 1: T1 5: XLXI_91/Q0 9: XLXN_16 2: XLXI_34/Q0 6: XLXI_91/Q1 10: XLXN_43 3: XLXI_34/Q1 7: XLXI_91/Q2 11: XLXN_44 4: XLXI_34/Q2 8: XLXN_13 12: XLXN_46 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs XLXN_144 ....XXX................................. 3 3 e .......X.XX............................. 3 3 XLXI_91/Q2 ....XX.................................. 2 2 XLXI_91/Q1 ....X................................... 1 1 d .......XXXX............................. 4 4 a .......XXXX............................. 4 4 XLXI_91/Q0 ........................................ 0 0 b .......X.XX............................. 3 3 g .......XXXX............................. 4 4 XLXI_34/Q2 .XX..................................... 2 2 XLXI_34/Q1 .X...................................... 1 1 XLXI_34/Q0 ........................................ 0 0 XLXN_13 ........XX.X............................ 3 3 T2 XXXX.................................... 4 4 XLXN_44 .......XXX.X............................ 4 4 XLXN_43 .......XXX.X............................ 4 4 T1 .XXX.................................... 3 3 XLXN_16 .......XXXXX............................ 5 5 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 11 I/O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 12 I/O (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 13 I/O (unused) 0 0 0 5 FB3_9 14 I/O XLXN_198 2 0 0 3 FB3_10 STD (b) (b) LED1 2 0 0 3 FB3_11 STD 18 I/O O XLXN_186 2 0 0 3 FB3_12 STD (b) (b) XLXI_93/Q2 2 0 0 3 FB3_13 STD (b) (b) IRED_OUT 1 0 0 4 FB3_14 STD 19 I/O O LED2 2 0 0 3 FB3_15 STD 20 I/O O LED4 2 0 0 3 FB3_16 STD 24 I/O O LED3 2 0 0 3 FB3_17 STD 22 I/O O XLXN_139 3 0 0 2 FB3_18 STD (b) (b) Signals Used by Logic in Function Block 1: S1 6: XLXN_103 10: XLXN_186 2: XLXI_92/Q0 7: XLXN_139 11: XLXN_197 3: XLXI_92/Q2 8: XLXN_140 12: XLXN_386 4: XLXI_93/Q0 9: XLXN_144 13: XLXN_388 5: XLXI_93/Q2 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs XLXN_198 ...XX.X..X.............................. 4 4 LED1 X....X.....XX........................... 4 4 XLXN_186 ...X..X................................. 2 2 XLXI_93/Q2 ...X..X..X.............................. 3 3 IRED_OUT .........XX............................. 2 2 LED2 X....X.....XX........................... 4 4 LED4 X....X.....XX........................... 4 4 LED3 X....X.....XX........................... 4 4 XLXN_139 .XX...XXX............................... 5 5 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 25 I/O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) LED5 2 0 0 3 FB4_5 STD 26 I/O O (unused) 0 0 0 5 FB4_6 (b) (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 27 I/O I (unused) 0 0 0 5 FB4_9 (b) XLXI_93/Q0 1 0 0 4 FB4_10 STD (b) (b) XLXN_388 2 0 0 3 FB4_11 STD 28 I/O I XLXI_92/Q0 2 0 0 3 FB4_12 STD (b) (b) XLXN_386 3 0 0 2 FB4_13 STD (b) (b) XLXN_140 3 0 0 2 FB4_14 STD 29 I/O I c 1 0 0 4 FB4_15 STD 33 I/O O XLXN_103 3 0 0 2 FB4_16 STD (b) (b) dp 1 0 0 4 FB4_17 STD 34 I/O O XLXI_92/Q2 3 0 0 2 FB4_18 STD (b) (b) Signals Used by Logic in Function Block 1: S1 6: XLXN_13 10: XLXN_386 2: SFH 7: XLXN_139 11: XLXN_388 3: XLXI_92/Q0 8: XLXN_140 12: XLXN_43 4: XLXN_103 9: XLXN_144 13: XLXN_44 5: XLXN_113 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs LED5 X..X.....XX............................. 4 4 XLXI_93/Q0 ......X................................. 1 1 XLXN_388 ...XX.....X............................. 3 3 XLXI_92/Q0 ......XXX............................... 3 3 XLXN_386 ...XX.....X............................. 3 3 XLXN_140 ..X...XXX............................... 4 4 c .....X.....XX........................... 3 3 XLXN_103 ...XX....XX............................. 4 4 dp .X...................................... 1 1 XLXI_92/Q2 ..X...XXX............................... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. IRED_OUT = XLXN_186 & XLXN_197; LED1 = S1 $ !XLXN_388 & !XLXN_103 & !XLXN_386; LED2 = S1 $ XLXN_388 & !XLXN_103 & !XLXN_386; LED3 = S1 $ !XLXN_388 & !XLXN_103 & XLXN_386; LED4 = S1 $ XLXN_388 & !XLXN_103 & XLXN_386; LED5 = S1 $ !XLXN_388 & XLXN_103 & !XLXN_386; MOSFET = S2; REL = !S3; T1.T = XLXI_34/Q0 & XLXI_34/Q1 & XLXI_34/Q2; T1.CLK = CLK_GEN; // GCK !T2.D = XLXI_34/Q0 & XLXI_34/Q1 & XLXI_34/Q2 $ T1; T2.CLK = CLK_GEN; // GCK XLXI_125/Q0.T = Vcc; XLXI_125/Q0.CLK = XLXN_198; XLXI_125/Q1.T = XLXI_125/Q0; XLXI_125/Q1.CLK = XLXN_198; XLXI_125/Q2.T = XLXI_125/Q0 & XLXI_125/Q1; XLXI_125/Q2.CLK = XLXN_198; XLXI_34/Q0.T = Vcc; XLXI_34/Q0.CLK = CLK_GEN; // GCK XLXI_34/Q1.T = XLXI_34/Q0; XLXI_34/Q1.CLK = CLK_GEN; // GCK XLXI_34/Q2.T = XLXI_34/Q0 & XLXI_34/Q1; XLXI_34/Q2.CLK = CLK_GEN; // GCK XLXI_91/Q0.T = Vcc; XLXI_91/Q0.CLK = CLK_GEN; // GCK XLXI_91/Q1.T = XLXI_91/Q0; XLXI_91/Q1.CLK = CLK_GEN; // GCK XLXI_91/Q2.T = XLXI_91/Q0 & XLXI_91/Q1; XLXI_91/Q2.CLK = CLK_GEN; // GCK XLXI_92/Q0.T = Vcc; XLXI_92/Q0.CLK = XLXN_144; XLXI_92/Q0.AR = XLXN_139 & XLXN_140; XLXI_92/Q2.T = XLXI_92/Q0 & XLXN_140; XLXI_92/Q2.CLK = XLXN_144; XLXI_92/Q2.AR = XLXN_139 & XLXN_140; XLXI_93/Q0.T = Vcc; XLXI_93/Q0.CLK = XLXN_139; XLXI_93/Q2.T = XLXI_93/Q0 & XLXN_186; XLXI_93/Q2.CLK = XLXN_139; XLXN_103.T = XLXN_388 & XLXN_386; XLXN_103.CLK = XLXN_113; XLXN_103.AR = XLXN_388 & XLXN_103; XLXN_113.T = Vcc; XLXN_113.CLK = CLK_FR; // GCK XLXN_13.T = Vcc; XLXN_13.CLK = XLXN_46; XLXN_13.AR = XLXN_43 & XLXN_16; XLXN_139.T = XLXI_92/Q0 & XLXN_140 & XLXI_92/Q2; XLXN_139.CLK = XLXN_144; XLXN_139.AR = XLXN_139 & XLXN_140; XLXN_140.T = XLXI_92/Q0; XLXN_140.CLK = XLXN_144; XLXN_140.AR = XLXN_139 & XLXN_140; XLXN_144.T = XLXI_91/Q0 & XLXI_91/Q1 & XLXI_91/Q2; XLXN_144.CLK = CLK_GEN; // GCK XLXN_16.T = XLXN_43 & XLXN_13 & XLXN_44; XLXN_16.CLK = XLXN_46; XLXN_16.AR = XLXN_43 & XLXN_16; XLXN_186.T = XLXI_93/Q0; XLXN_186.CLK = XLXN_139; XLXN_197.T = XLXI_125/Q0 & XLXI_125/Q1 & XLXI_125/Q2; XLXN_197.CLK = XLXN_198; XLXN_198.T = XLXI_93/Q0 & XLXN_186 & XLXI_93/Q2; XLXN_198.CLK = XLXN_139; XLXN_386.T = XLXN_388; XLXN_386.CLK = XLXN_113; XLXN_386.AR = XLXN_388 & XLXN_103; XLXN_388.T = Vcc; XLXN_388.CLK = XLXN_113; XLXN_388.AR = XLXN_388 & XLXN_103; XLXN_43.T = XLXN_13; XLXN_43.CLK = XLXN_46; XLXN_43.AR = XLXN_43 & XLXN_16; XLXN_44.T = XLXN_43 & XLXN_13; XLXN_44.CLK = XLXN_46; XLXN_44.AR = XLXN_43 & XLXN_16; XLXN_46.T = Vcc; XLXN_46.CLK = CLK; // GCK a = !XLXN_43 & !XLXN_13 & XLXN_44 # !XLXN_43 & XLXN_13 & !XLXN_44 & !XLXN_16; b = XLXN_43 & !XLXN_13 & XLXN_44 # !XLXN_43 & XLXN_13 & XLXN_44; c = XLXN_43 & !XLXN_13 & !XLXN_44; d = XLXN_43 & XLXN_13 & XLXN_44 # !XLXN_43 & !XLXN_13 & XLXN_44 # !XLXN_43 & XLXN_13 & !XLXN_44 & !XLXN_16; dp = SFH; e = XLXN_13 # !XLXN_43 & XLXN_44; f = XLXN_43 & XLXN_13 # XLXN_43 & !XLXN_44 # XLXN_13 & !XLXN_44 & !XLXN_16; g = XLXN_43 & XLXN_13 & XLXN_44 # !XLXN_43 & !XLXN_44 & !XLXN_16; **************************** Device Pin Out **************************** Device : XC9572XL-10-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572XL-10-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 f 23 GND 2 REL 24 LED4 3 TIE 25 TIE 4 MOSFET 26 LED5 5 CLK_GEN 27 S3 6 CLK_FR 28 S2 7 CLK 29 S1 8 TIE 30 TDO 9 SFH 31 GND 10 GND 32 VCC 11 TIE 33 c 12 TIE 34 dp 13 TIE 35 e 14 TIE 36 d 15 TDI 37 a 16 TMS 38 b 17 TCK 39 g 18 LED1 40 TIE 19 IRED_OUT 41 VCC 20 LED2 42 T2 21 VCC 43 TIE 22 LED3 44 T1 Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25