Timing Report

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Design Name test_pcb
Device, Speed (SpeedFile Version) XC9572XL, -10 (3.0)
Date Created Sat Jun 14 13:28:45 2008
Created By Timing Report Generator: version G.28
Copyright Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for XLXN_198.Q
Clock to Setup (tCYC) 10.000 ns.
Pad to Pad Delay (tPD) 10.000 ns.
Clock Pad to Output Pad Delay (tCO) 37.200 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK_FR 111.111 Limited by Clock Pulse Width for CLK_FR
XLXN_198.Q 71.429 Limited by Clock Pulse Width for XLXN_198.Q
CLK 111.111 Limited by Clock Pulse Width for CLK
XLXN_139.Q 71.429 Limited by Clock Pulse Width for XLXN_139.Q
CLK_GEN 100.000 Limited by Cycle Time for CLK_GEN
XLXN_144.Q 71.429 Limited by Clock Pulse Width for XLXN_144.Q
XLXN_113.Q 71.429 Limited by Clock Pulse Width for XLXN_113.Q
XLXN_46.Q 71.429 Limited by Clock Pulse Width for XLXN_46.Q

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock CLK_FR to Pad
Destination Pad Clock (edge) to Pad
LED1 21.400
LED2 21.400
LED3 21.400
LED4 21.400
LED5 21.400

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
a 21.400
b 21.400
c 21.400
d 21.400
e 21.400
f 21.400
g 21.400

Clock CLK_GEN to Pad
Destination Pad Clock (edge) to Pad
IRED_OUT 37.200
T1 5.800
T2 5.800


Clock to Setup Times for Clocks

Clock to Setup for clock XLXN_198.Q
Source Destination Delay
XLXI_125/Q0.Q XLXI_125/Q1.D 10.000
XLXI_125/Q0.Q XLXI_125/Q2.D 10.000
XLXI_125/Q0.Q XLXN_197.D 10.000
XLXI_125/Q1.Q XLXI_125/Q2.D 10.000
XLXI_125/Q1.Q XLXN_197.D 10.000
XLXI_125/Q2.Q XLXN_197.D 10.000

Clock to Setup for clock XLXN_139.Q
Source Destination Delay
XLXI_93/Q0.Q XLXI_93/Q2.D 10.000
XLXI_93/Q0.Q XLXN_186.D 10.000
XLXI_93/Q0.Q XLXN_198.D 10.000
XLXI_93/Q2.Q XLXN_198.D 10.000
XLXN_186.Q XLXI_93/Q2.D 10.000
XLXN_186.Q XLXN_198.D 10.000

Clock to Setup for clock CLK_GEN
Source Destination Delay
T1.Q T2.D 10.000
XLXI_34/Q0.Q T1.D 10.000
XLXI_34/Q0.Q T2.D 10.000
XLXI_34/Q0.Q XLXI_34/Q1.D 10.000
XLXI_34/Q0.Q XLXI_34/Q2.D 10.000
XLXI_34/Q1.Q T1.D 10.000
XLXI_34/Q1.Q T2.D 10.000
XLXI_34/Q1.Q XLXI_34/Q2.D 10.000
XLXI_34/Q2.Q T1.D 10.000
XLXI_34/Q2.Q T2.D 10.000
XLXI_91/Q0.Q XLXI_91/Q1.D 10.000
XLXI_91/Q0.Q XLXI_91/Q2.D 10.000
XLXI_91/Q0.Q XLXN_144.D 10.000
XLXI_91/Q1.Q XLXI_91/Q2.D 10.000
XLXI_91/Q1.Q XLXN_144.D 10.000
XLXI_91/Q2.Q XLXN_144.D 10.000

Clock to Setup for clock XLXN_144.Q
Source Destination Delay
XLXI_92/Q0.Q XLXI_92/Q2.D 10.000
XLXI_92/Q0.Q XLXN_139.D 10.000
XLXI_92/Q0.Q XLXN_140.D 10.000
XLXI_92/Q2.Q XLXN_139.D 10.000
XLXN_140.Q XLXI_92/Q2.D 10.000
XLXN_140.Q XLXN_139.D 10.000

Clock to Setup for clock XLXN_113.Q
Source Destination Delay
XLXN_386.Q XLXN_103.D 10.000
XLXN_388.Q XLXN_103.D 10.000
XLXN_388.Q XLXN_386.D 10.000

Clock to Setup for clock XLXN_46.Q
Source Destination Delay
XLXN_13.Q XLXN_16.D 10.000
XLXN_13.Q XLXN_43.D 10.000
XLXN_13.Q XLXN_44.D 10.000
XLXN_43.Q XLXN_16.D 10.000
XLXN_43.Q XLXN_44.D 10.000
XLXN_44.Q XLXN_16.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
S1 LED1 10.000
S1 LED2 10.000
S1 LED3 10.000
S1 LED4 10.000
S1 LED5 10.000
S2 MOSFET 10.000
S3 REL 10.000
SFH dp 10.000



Number of paths analyzed: 0
Number of Timing errors: 0
Analysis Completed: Sat Jun 14 13:28:45 2008